The Cortex-R7 MPCore processor can support the following power domains:
One for each of the processors.
One for each of the individual processor Cache RAM arrays, including the Branch Predictor (BP) RAMs.
One for each of the individual processor TCM RAM arrays.
One for the SCU duplicated tag RAMs.
One for the remaining logic, the SCU logic cells, and private peripherals.
If the ETM is included, each ETM for each processor has its own power domain. In addition, the local CoreSight logic, that is, CTI0 and CTI1, CTM, APB multiplexer, and ROM table, are also in a separate power domain.
Each power domain has its own clock and reset signal, and its own clock off signal. When a power domain is powered-off, some clamp values might be driven HIGH. See the ARM® Cortex®-R7 MPCore Configuration and Sign-off Guide for more information.