The SCU CPU Power Status Register characteristics are:
Specifies the state of the Cortex-R7 processors with reference to power modes.
- Usage constraints
Writes to this register are enabled when the access bit for the processor is set in the SCU Access Control Register. See SCU Access Control Register.
Dormant mode and powered-off mode are controlled by an external power controller. SCU CPU Status Register bits indicate to the external power controller the power domains that can be powered down.
Before entering any other power mode than Normal, the processor must set its status field to signal to the power controller the mode it is about to enter. The processor powerdown routine must then execute a DSB instruction and then a WFI entry instruction. When in WFI state, the PWRCTLOn bus is enabled and signals to the power controller what it must do with power domains. See also Individual processor power management.
The SCU CPU Power Status Register bits can also be read by a processor exiting low-power mode to determine its state before executing its reset setup.
Available in all configurations.
See the register summary in Table 9.2.
Figure 9.4 shows the SCU CPU Power Status Register bit assignments.
Table 9.5 shows the SCU CPU Power Status Register bit assignments.
|[9:8]||Processor 1 status|
Power status of processor 1:
|[1:0]||Processor 0 status|
Power status of processor 0: