The TRCPDSR characteristics are:
Figure 3.48 shows the TRCPDSR bit assignments.
Table 3.59 shows the TRCPDSR bit assignments.
|||OSLK||OS lock status.|
Sticky power down state.
This bit is set to 1 when power to the ETM-R7 registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR.
Indicates the ETM-R7 is powered:
If a system implementation allows the ETM to be powered off independently of the debug power domain, the system must handle accesses to the ETM appropriately.