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1.3. Features

ETM-R7 supports tracing of 32-bit ARM instructions, and 16-bit and 32-bit Thumb instructions.

See the Embedded Trace Macrocell Architecture Specification ETMv4 for information about:

  • The trace protocol.

  • The features of ETMv4.

  • Controlling tracing using triggering and filtering resources.

  • ETM sharing.

Table 1.1 shows the features of the ETM-R7 that are implementation-defined, in terms of either:

  • The number of times the feature is implemented.

  • The size of the feature.

Table 1.1. ETM-R7 features with implementation-defined number of instances or size
FeatureETM-R7 valueNotes
Address comparators4 pairsSee bits[3:0] of the ID Register 4
Data value comparators2See bits[7:4] of the ID Register 4  
Context ID comparators1See bits[27:24] of the ID Register 4
Single-Shot comparator resource2, one for instruction, one for dataSee bits[2:0] of the Single-Shot Comparator Status Registers 0-1
Counters2See bits[30:28] of the ID Register 5
Cycle count size12See bits[28:25] of the ID Register 2
Sequencer1One four-state sequencer. See bits[27:25] of the ID Register 5. 
Processor comparator inputsNot implementedSee bits[15:12] of the ID Register 4
External inputs64See bits[8:0] of the ID Register 5
External outputs4See bits[3:0] of the Event Control 1 Register
External input selectors4 See bits[11:9] of the ID Register 5
Resource selector pairs8See bits[19:16] of the ID Register 4
Instruction trace port size32-bit-
Data trace port size64-bit-
Instruction FIFO[a]128 byte with 32-bit outputUses ATB
Data FIFO256 byte with 64-bit outputUses ATB
Claim tag bits4See bits[3:0] of the Claim Tag Set Register

[a] Instruction trace can be configured to take priority over data trace. See bit[10] of the TRCSTALLCTLR.

Table 1.2 shows the optional features of the ETM architecture that the ETM-R7 implements.

Table 1.2. ETM-R7 implementation of optional features
Configurable FIFO No-
Trace Start/Stop blockYesViewInst Start/Stop Control Register
Trace all branches optionYesSee bit[5] of the ID Register 0
Trace of conditional instructionsYesSee bits[13:12] and bit [6] of the ID Register 0, using the full CPSR value
Cycle counting in instruction traceYesSee bit[7] of the ID Register 0
Data trace supported YesSee bits[4:3] of the ID Register 0
Data address comparisonYesSee bit[8] of the ID Register 4
OS Lock mechanismYesOS Lock Access Register
Secure non-invasive debugNoThe Cortex-R7 MPCore processor does not implement the Security Extensions
Context ID tracingYesSee bits[9:5] of the ID Register 2
Trace outputYesATB
Timestamp size (48/64)System configurableSee bits[28:24] of the ID Register 0
Memory mapped access to ETM registersYes-
System instruction access to ETM registersNo-
VMID comparator supportNoSee bits[31:28] of the ID Register 4
ATB trigger supportYesSee bit[22] of the ID Register 5

See Appendix A Signal Descriptions for information about the macrocell signals.

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