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3.4.30. ID Register 0

The TRCIDR0 characteristics are:

Purpose

Indicates the tracing capabilities of the ETM-R7.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1 and Table 3.5.

Figure 3.36 shows the TRCIDR0 bit assignments.

Figure 3.36. TRCIDR0 bit assignments

Figure 3.36. TRCIDR0 bit assignments

Table 3.46 shows the TRCIDR0 bit assignments.

Table 3.46. TRCIDR0 bit assignments
BitsNameFunction
[31:30]-RAZ/WI
[29]COMMOPT

Indicates the meaning of the commit field in some packets:

b0

Commit mode 0.

[28:24]TSSIZE

Global timestamp size. Driven from external TSSIZE pin:

b00110

Maximum of 48-bit global timestamp implemented. TSSIZE is LOW.

b01000

Maximum of 64-bit global timestamp implemented. TSSIZE is HIGH.

Other values are Reserved.

[23:17]-RAZ/WI
[16:15]QSUPP

Indicates Q element support:

b00

Q elements not supported.

[14]QFILT

Indicates Q element filtering support:

b0

Q element filtering not supported.

[13:12]CONDTYPE

Indicates how conditional results are traced:

b01

Full CPSR traced.

[11:10]NUMEVENT

Number of events supported in the trace, minus 1:

b11

Four events supported.

[9]RETSTACK

Return stack support:

1

Return stack implemented.

[8]-RAZ/WI
[7]TRCCCI

Support for cycle counting in the instruction trace:

1

Cycle counting in the instruction trace is implemented.

[6]TRCCOND

Support for conditional instruction tracing:

1

Conditional instruction tracing is implemented.

[5]TRCBB

Support for branch broadcast tracing:

1

Branch broadcast tracing is implemented.

[4:3]TRCDATA

Support for tracing of data:

b11

Tracing of data addresses and data values is implemented.

[2:1]INSTP0

Support for tracing of load and store instructions as P0 elements:

b11

Tracing of load and store instructions as P0 elements is implemented.

[0]-RAO/WI

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