The TRCIDR3 characteristics are:
Figure 3.39 shows the TRCIDR3 bit assignments.
Table 3.49 shows the TRCIDR3 bit assignments.
Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:
|[30:28]||NUMPROC||Number of processors available for tracing minus 1, indicating 1-8 processors. This describes the largest valid value which can be written to TRCPROCSELR.|
System support for stall control of the processor. This is driven from the ETM SYSSTALL input pin, reflecting the system implementation:
This field is used in conjunction with STALLCTL. Only when both SYSSTALL and STALLCTL are b1 does the system support stalling of the processor.
Stall control support:
This field is used in conjunction with SYSSTALL.
Synchronization period support:
Indicates whether TRCVICTLR.TRCERR is implemented:
Exception levels implemented in Non-Secure state. One bit for each exception level 0-3.
Exception levels implemented in Secure state. One bit for each exception level 0-3.
Instruction trace cycle counting minimum threshold: