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3.4.33. ID Register 3

The TRCIDR3 characteristics are:

Purpose

Indicates certain aspects of the ETM-R7 configuration.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1 and Table 3.5.

Figure 3.39 shows the TRCIDR3 bit assignments.

Figure 3.39. TRCIDR3 bit assignments

Figure 3.39. TRCIDR3 bit assignments

Table 3.49 shows the TRCIDR3 bit assignments.

Table 3.49. TRCIDR3 bit assignments
BitsNameFunction
[31]NOOVERFLOW

Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:

0

NOOVERFLOW is not implemented.

[30:28]NUMPROCNumber of processors available for tracing minus 1, indicating 1-8 processors. This describes the largest valid value which can be written to TRCPROCSELR.
[27]SYSSTALL

System support for stall control of the processor. This is driven from the ETM SYSSTALL input pin, reflecting the system implementation:

0

System does not support stall control of the processor.

1

System supports stall control of the processor.

This field is used in conjunction with STALLCTL. Only when both SYSSTALL and STALLCTL are b1 does the system support stalling of the processor.

[26]STALLCTL

Stall control support:

1

TRCSTALLCTLR is implemented.

This field is used in conjunction with SYSSTALL.

[25]SYNCPR

Synchronization period support:

0

TRCSYNCPR is read-write.

[24]TRCERR

Indicates whether TRCVICTLR.TRCERR is implemented:

1

TRCERR is implemented.

[23:20]EXLEVEL_NS

Exception levels implemented in Non-Secure state. One bit for each exception level 0-3.

b0000

No Non-Secure exception levels are implemented.

[19:16]EXLEVEL_S

Exception levels implemented in Secure state. One bit for each exception level 0-3.

b1001

Secure exception levels EL0 and EL3 are implemented.

[15:12]-RAZ/WI
[11:0]CCITMIN

Instruction trace cycle counting minimum threshold:

0x4

Minimum threshold is 4.


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