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3.4.61. Integration Test Registers

The following subsections describe the Integration Test Registers. To access these registers you must first set bit [0] of the Integration Mode Control Register to 1.

  • You can use the write-only Integration Test Registers to set the outputs of some of the ETM signals. Table 3.79 shows the signals that can be controlled in this way.

  • You can use the read-only Integration Test Registers to read the state of some of the ETM input signals. Table 3.80 shows the signals that can be read in this way.

See the Embedded Trace Macrocell Architecture Specification ETMv4 for details of TRCITCTRL.

Table 3.79. Output signals that the Integration Test Registers can control
SignalRegisterBitsRegister description
AFREADYMDTRCITDATBOUTR[1]See Integration Data ATB Out Register
AFREADYMITRCITIATBOUTR[1]See Integration Instruction ATB Out Register
ATBYTESMD[2:0]TRCITDATBOUTR[10:8]See Integration Data ATB Out Register
ATBYTESMI[1:0]TRCITIATBOUTR[9:8]See Integration Instruction ATB Out Register
ATDATAMD[63, 55, 47, 39, 31, 23, 15, 7, 0]TRCITDDATAR[8:0]See Integration Data ATB Data Register
ATDATAMI[31, 23, 15, 7, 0]TRCITIDATAR[4:0]See Integration Instruction ATB Data Register
ATIDMD[6:0]TRCITATBIDR[6:0]See Integration ATB Identification Register
ATIDMI[6:0]TRCITATBIDR[6:0]See Integration ATB Identification Register
ATVALIDMDTRCITDATBOUTR[0]See Integration Data ATB Out Register
ATVALIDMITRCITIATBOUTR[0]See Integration Instruction ATB Out Register
ETMACTIVETRCITMISCOUTR[5]See Integration Miscellaneous Outputs Register
ETMEXTOUT[3:0]TRCITMISCOUTR[11:8]See Integration Miscellaneous Outputs Register

Table 3.80. Input signals that the Integration Test Registers can read
SignalRegisterBitsRegister description
AFVALIDMDTRCITDATBINR[1]See Integration Data ATB In Register
ATREADYMDTRCITDATBINR[0]See Integration Data ATB In Register
AFVALIDMITRCITIATBINR[1]See Integration Instruction ATB In Register
ATREADYMITRCITIATBINR[0]See Integration Instruction ATB In Register
CPUACTIVETRCITMISCINR[4]See Integration Miscellaneous Inputs Register
DBGACKTRCITMISCINR[5]See Integration Miscellaneous Inputs Register
ETMEVENT[3:0]TRCITMISCINR[3:0]See Integration Miscellaneous Inputs Register

Using the Integration Test Registers

The Cortex‑R7 MPCore Integration Manual gives a full description of the use of the Integration Test Registers to check integration. In brief:

When bit[0] of TRCITCTRL is set to 1:

  • Values written to the write-only integration test registers map onto the specified outputs of the macrocell. For example, writing 0x3 TRCITMISCOUTR[11:8] causes ETMEXTOUT[3:0] to take the value 0x3.

  • Values read from the read-only integration test registers correspond to the values of the specified inputs of the macrocell. For example, if you read TRCITMISCINR[3:0] you obtain the value of ETMEXTIN[3:0].

When bit[0] of TRCITCTRL is set to 0:

  • Reading an Integration Test Register returns an unpredictable value.

  • The effect of attempting to write to an Integration Test Register, other than the read-only Integration Test Registers, is unpredictable.

    Note

    You must not attempt to write to an Integration Test Register unless you have set bit[0] of TRCITCTRL to 1.

Integration Miscellaneous Outputs Register

The TRCITMISCOUTR characteristics are:

Purpose

Sets the state of the output pins shown in Table 3.81.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The value of the register sets the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.79.

Figure 3.69 shows the TRCITMISCOUTR bit assignments.

Figure 3.69. TRCITMISCOUTR bit assignments

Figure 3.69. TRCITMISCOUTR bit assignments

Table 3.81 shows the TRCITMISCOUTR bit assignments.

Table 3.81. TRCITMISCOUTR bit assignments
BitsNameFunction
[31:12]-Reserved. Write as zero.
[11:8]EXTOUTDrives the ETMEXTOUT[3:0] output pins[a].
[7:6]-Reserved. Write as zero.
[5]ACTIVE

Drives the ETMACTIVE output pin[a].

[4:0]-Reserved. Write as zero.

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The TRCITMISCOUTR bit values correspond to the physical state of the output pins.


Integration Miscellaneous Inputs Register

The TRCITMISCINR characteristics are:

Purpose

Reads the state of the input pins shown in Table 3.82.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The values of the register bits depend on the signals on the input pins when the register is read.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.80.

Figure 3.70 shows the TRCITMISCINR bit assignments.

Figure 3.70. TRCITMISCINR bit assignments

Figure 3.70. TRCITMISCINR bit assignments

Table 3.82 shows the TRCITMISCINR bit assignments.

Table 3.82. TRCITMISCINR bit assignments
BitsNameFunction
[31:6]-Reserved. Read undefined.
[5]DBGACKReturns the value of the DBGACK input pin[a].
[4]CPUACTIVEReturns the value of the CPUACTIVE input pin[a].
[3:0]EXTINReturns the value of the ETMEVENT[3:0] input pins[a].

[a] When an input pin is LOW, the corresponding register bit is 0.

When an input pin is HIGH, the corresponding register bit is 1.

The TRCITMISCINR bit values always correspond to the physical state of the input pins.


Integration ATB Identification Register

The TRCITATBIDR characteristics are:

Purpose

Sets the state of output pins shown in Table 3.83.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The value of the register sets the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.79.

Figure 3.71 shows the TRCITATBIDR bit assignments.

Figure 3.71. TRCITATBIDR bit assignments

Figure 3.71. TRCITATBIDR bit assignments

Table 3.83 shows the TRCITATBIDR bit assignments.

Table 3.83. TRCITATBIDR bit assignments
BitsNameFunction
[31:7]-Reserved. Read undefined.
[6:0]IDDrives the ATIDMD[6:0] and ATIDMI[6:0] output pins[a].

[a] Bits[6:1] drive both ATIDMD[6:1] and ATIDMI[6:1]. Bit 0] drives ATIDMI[0].

When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

ATIDMD[0] is always driven HIGH.

The TRCITATBIDR bit values correspond to the physical state of the output pins.


Integration Data ATB Data Register

The TRCITDDATAR characteristics are:

Purpose

Sets the state of the ATDATAMD output pins shown in Table 3.84.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The value of the register sets the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.79.

Figure 3.72 shows the TRCITDDATAR bit assignments.

Figure 3.72. TRCITDDATAR bit assignments

Figure 3.72. TRCITDDATAR bit assignments

Table 3.84 shows the TRCITDDATAR bit assignments.

Table 3.84. TRCITDDATAR bit assignments
BitsNameFunction
[31:9]-Reserved. Write as zero.
[8:0]ATDATAMD Drives the ATDATAMD[63, 55, 47, 39, 31, 23, 15, 7, 0] output pins[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The TRCITDDATAR bit values correspond to the physical state of the output pins.


Integration Instruction ATB Data Register

The TRCITIDATAR characteristics are:

Purpose

Sets the state of the ATDATAMI output pins shown in Table 3.85.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The value of the register sets the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.79.

Figure 3.73 shows the TRCITIDATAR bit assignments.

Figure 3.73. TRCITIDATAR bit assignments

Figure 3.73. TRCITIDATAR bit assignments

Table 3.85 shows the TRCITIDATAR bit assignments.

Table 3.85. TRCITIDATAR bit assignments
BitsNameFunction
[31:5]-Reserved. Write as zero.
[4:0]ATDATAMIDrives the ATDATAMI[31, 23, 15, 7, 0] output pins[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The TRCITIDATAR bit values correspond to the physical state of the output pins.


Integration Data ATB In Register

The TRCITDATBINR characteristics are:

Purpose

Reads the state of the input pins shown in Table 3.86.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The values of the register bits depend on the signals on the input pins when the register is read.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.80.

Figure 3.74 shows the TRCITDATBINR bit assignments.

Figure 3.74. TRCITDATBINR bit assignments

Figure 3.74. TRCITDATBINR bit assignments

Table 3.86 shows the TRCITDATBINR bit assignments.

Table 3.86. TRCITDATBINR bit assignments
BitsNameFunction
[31:2]-Reserved. Read undefined.
[1]AFVALIDMReturns the value of the AFVALIDMD input pin[a].
[0]ATREADYMReturns the value of the ATREADYMD input pin[a].

[a] When an input pin is LOW, the corresponding register bit is 0.

When an input pin is HIGH, the corresponding register bit is 1.

The TRCITDATBINR bit values always correspond to the physical state of the input pins.


Integration Instruction ATB In Register

The TRCITIATBINR characteristics are:

Purpose

Reads the state of the input pins shown in Table 3.87.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The values of the register bits depend on the signals on the input pins when the register is read.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.80.

Figure 3.75 shows the TRCITIATBINR bit assignments.

Figure 3.75. TRCITIATBINR bit assignments

Figure 3.75. TRCITIATBINR bit assignments

Table 3.87 shows the TRCITIATBINR bit assignments.

Table 3.87. TRCITIATBINR bit assignments
BitsNameFunction
[31:2]-Reserved. Read undefined.
[1]AFVALIDMReturns the value of the AFVALIDMI input pin[a].
[0]ATREADYMReturns the value of the ATREADYMI input pin[a].

[a] When an input pin is LOW, the corresponding register bit is 0.

When an input pin is HIGH, the corresponding register bit is 1.

The TRCITIATBINR bit values always correspond to the physical state of the input pins.


Integration Data ATB Out Register

The TRCITDATBOUTR characteristics are:

Purpose

Sets the state of the output pins shown in Table 3.88.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The value of the register sets the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.79.

Figure 3.76 shows the TRCITDATBOUTR bit assignments.

Figure 3.76. TRCITDATBOUTR bit assignments

Figure 3.76. TRCITDATBOUTR bit assignments

Table 3.88 shows the TRCITDATBOUTR bit assignments.

Table 3.88. TRCITDATBOUTR bit assignments
BitsNameFunction
[31:11]-Reserved. Read undefined.
[10:8]BYTESDrives the ATBYTESMD[2:0] output pins[a].
[7:2]-Reserved. Read undefined.
[1]AFREADYDrives the AFREADYMD output pin[a].
[0]ATVALIDDrives the ATVALIDMD output pin[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The TRCITDATBOUTR bit values always correspond to the physical state of the output pins.


Integration Instruction ATB Out Register

The TRCITIATBOUTR characteristics are:

Purpose

Sets the state of the output pins shown in Table 3.89.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.

  • The value of the register sets the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.10, and Table 3.79.

Figure 3.77 shows the TRCITIATBOUTR bit assignments.

Figure 3.77. TRCITIATBOUTR bit assignments

Figure 3.77. TRCITIATBOUTR bit assignments

Table 3.89 shows the TRCITIATBOUTR bit assignments.

Table 3.89. TRCITIATBOUTR bit assignments
BitsNameFunction
[31:10]-Reserved. Read undefined.
[9:8]BYTESDrives the ATBYTESMI[1:0] output pins[a].
[7:2]-Reserved. Read undefined.
[1]AFREADYDrives the AFREADYMI output pin[a].
[0]ATVALIDDrives the ATVALIDMI output pin[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The TRCITIATBOUTR bit values always correspond to the physical state of the output pins.


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