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3.4.38. Single-Shot Comparator Status Registers 0-1

The TRCSSCSRn characteristics are:

Purpose

Indicates the status of the single-shot comparators:

  • TRCSSCSR0 is sensitive to instruction addresses.

  • TRCSSCSR1 is sensitive to data addresses and values.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1 and Table 3.7.

Figure 3.44 shows the TRCSSCSRn bit assignments.

Figure 3.44. TRCSSCSRn bit assignments

Figure 3.44. TRCSSCSRn bit assignments

Table 3.54 shows the TRCSSCSR0 bit assignments.

Table 3.54. TRCSSCSR0 bit assignments
BitsNameFunction
[31]STATUS

Single-shot status. This indicates whether any of the selected comparators have matched:

0

Match has not occurred.

1

Match has occurred at least once.

When programming the ETM-R7, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control.

[30:3}-RAZ/WI
[2]DV

Data value comparator support:

0

Single-shot data value comparisons not supported.

[1]DA

Data address comparator support:

0

Single-shot data address comparisons not supported.

[0]INST

Instruction address comparator support:

1

Single-shot instruction address comparisons supported.


Table 3.55 shows the TRCSSCSR1 bit assignments.

Table 3.55. TRCSSCSR1 bit assignments
BitsNameFunction
[31]STATUS

Single-shot status. This indicates whether any of the selected comparators have matched:

0

Match has not occurred.

1

Match has occurred at least once.

When programming the ETM-R7, this bit must be explicitly written to 0 to enable this single-shot comparator control.

[30:3}-RAZ/WI
[2]DV

Data value comparator support:

1

Single-shot data value comparisons supported.

[1]DA

Data address comparator support:

1

Single-shot data address comparisons supported.

[0]INST

Instruction address comparator support:

0

Single-shot instruction address comparisons not supported.


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