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3.4.8. Stall Control Register

The TRCSTALLCTLR characteristics are:

Purpose

Enables the ETM-R7 to stall the Cortex-R7 MPCore processor if the ETM-R7 FIFO overflows.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1 and Table 3.2.

Figure 3.9 shows the TRCSTALLCTLR bit assignments.

Figure 3.9. TRCSTALLCTLR bit assignments

Figure 3.9. TRCSTALLCTLR bit assignments

Table 3.19 shows the TRCSTALLCTLR bit assignments.

Table 3.19. TRCSTALLCTLR bit assignments
BitsNameFunction
[31:13]-RAZ/WI
[12:11]DATADISCARD

Sets the priority of data trace components, enabling the ETM-R7 to discard some data if the data trace buffer space is less than LEVEL:

b00

Discard no data.

b01

Discard loaded data transfers.

b10

Discard stored data transfers.

b11

Discard both loaded and stored data transfers.

[10]INSTPRIORITY

Prioritize instruction trace if instruction trace buffer space is less than LEVEL:

0

Do not prioritize instruction trace.

1

Prioritize instruction trace.

[9]DSTALL

Stall processor based on data trace buffer space:

0

Do not stall processor.

1

Stall processor if data trace buffer space is less than LEVEL.

[8]ISTALL

Stall processor based on instruction trace buffer space:

0

Do not stall processor.

1

Stall processor if instruction trace buffer space is less than LEVEL.

[7:4]-RAZ/WI
[3:2]LEVEL

Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow:

b00

Lowest level, where zero invasion occurs.

b11

Highest level, where the most invasion occurs to reduce the risk of overflow.

[1:0]-RAZ/WI

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