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3.4.14. ViewInst Main Control Register

The TRCVICTLR characteristics are:

Purpose

Controls instruction trace filtering.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1 and Table 3.3.

Figure 3.15 shows the TRCVICTLR bit assignments.

Figure 3.15. TRCVICTLR bit assignments

Figure 3.15. TRCVICTLR bit assignments

Table 3.25 shows the TRCVICTLR bit assignments.

Table 3.25. TRCVICTLR bit assignments
BitsValueFunction
[31:20]-RAZ/WI
[19]EXLEVEL_S3

Disables tracing in the specified exception level in Secure state for exception level 3.

0

Enable ViewInst in this exception level.

1

Disable ViewInst in this exception level.

[18:17]-RAZ/WI
[16]EXLEVEL_S0

Disables tracing in the specified exception level in Secure state for exception level 0.

0

Enable ViewInst in this exception level.

1

Disable ViewInst in this exception level.

[15:12]-RAZ/WI
[11]TRCERR

Selects whether a system error exception must always be traced:

0

System error exception is traced only if the instruction or exception immediately before the system error exception is traced.

1

System error exception is always traced regardless of the value of ViewInst.

[10]TRCRESET

Selects whether a reset exception must always be traced:

0

Reset exception is traced only if the instruction or exception immediately before the reset exception is traced.

1

Reset exception is always traced regardless of the value of ViewInst.

[9]SSSTATUS

Indicates the current status of the start/stop logic:

0

Start/stop logic is in the stopped state.

1

Start/stop logic is in the started state.

[8]-RAZ/WI
[7]TYPE

Selects the resource type:

0

Single selected resource.

1

Boolean combined resource pair.

[6:4]-RAZ/WI
[3:0]SEL

Selects the resource number, based on the value of TYPE:

When TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].


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