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3.4.16. ViewInst Start/Stop Control Register

The TRCVISSCTLR characteristics are:

Purpose

Defines the single address comparators that control the ViewInst Start/Stop logic.

Usage constraints

Can only be written when the ETM-R7 is disabled.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1 and Table 3.3.

Figure 3.17 shows the TRCVISSCTLR bit assignments.

Figure 3.17. TRCVISSCTLR bit assignments

Figure 3.17. TRCVISSCTLR bit assignments

Table 3.27 shows the TRCVISSCTLR bit assignments.

Table 3.27. TRCVISSCTLR bit assignments
BitsNameFunction
[31:24]-RAZ/WI
[23:16]STOP

Defines the single address comparators to stop trace with the ViewInst Start/Stop control.

One bit is provided for each implemented single address comparator.

[15:8]-RAZ/WI
[7:0]START

Defines the single address comparators to start trace with the ViewInst Start/Stop control.

One bit is provided for each implemented single address comparator.


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