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3.3. Register summary

This section summarizes the ETM registers. For full descriptions of the ETM registers, see:

  • Register descriptions, for the implementation-defined registers.

  • the Embedded Trace Macrocell Architecture Specification ETMv4, for the other registers.

Table 3.1 shows the ETM registers in numerical order and describes each register.

The macrocell registers are listed by functional group in Functional grouping of registers. The functional group register tables include additional information about each register:

  • The register access type. This is read-only, write-only or read and write.

  • The base offset address of the register. The base address of a register is always four times its register number.

  • Additional information about the implementation of the register, where appropriate.

Note

  • Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.

  • In Table 3.1:

    • The Reset value column shows the value of the register immediately after an ETM reset. For read-only registers, every read of the register returns this value.

    • Access type is described as follows:

      RW

      Read and write.

      RO

      Read only.

      WO

      Write only.

All ETM registers are 32 bits wide.

Table 3.1. ETM-R7 register summary
Register numberBase offsetNameTypeReset valueDescription
10x004TRCPRGCTLR RW0x00000000Programming Control Register
20x008TRCPROCSELRRW0x00000000Processor Select Control Register
30x00CTRCSTATRRO-Status Register
40x010TRCCONFIGRRW-Trace Configuration Register
60x018TRCAUXCTLRRW0x00000000Auxiliary Control Register
80x020TRCEVENTCTL0RRW-Event Control 0 Register
90x024TRCEVENTCTL1RRW-Event Control 1 Register
110x02CTRCSTALLCTLRRW-Stall Control Register
120x030TRCTSCTLRRW-Global Timestamp Control Register
130x034TRCSYNCPRRW-Synchronization Period Register
140x038TRCCCCTLRRW-Cycle Count Control Register
150x03CTRCBBCTLRRW-Branch Broadcast Control Register
160x040TRCTRACEIDRRW-Trace ID Register
320x080TRCVICTLRRW-ViewInst Main Control Register
330x084TRCVIIECTLRRW-ViewInst Include/Exclude Control Register
340x088TRCVISSCTLRRW-ViewInst Start/Stop Control Register
400x0A0TRCVDCTLRRW-ViewData Main Control Register
410x0A4TRCVDSACCTLRRW-ViewData Include/Exclude Single Address Comparator Register
420x0A8TRCVDARCCTLRRW-ViewData Include/Exclude Address Range Comparator Register
64-66

0x100-0x108

TRCSEQEVRnRW-Sequencer State Transition Control Registers 0-2
700x118 TRCSEQRSTEVRRW-Sequencer Reset Control Register
710x11C TRCSEQSTRRW-Sequencer State Register
720x120 TRCEXTINSELRRW-External Input Select Register
80-81

0x140-0x144

TRCCNTRLDVRnRW-Counter Reload Value Registers 0-1
84

0x150

TRCCNTCTLR0RW-Counter Control Register 0
85

0x154

TRCCNTCTLR1RW-Counter Control Register 1
88-89

0x160-0x164

TRCCNTVRnRW-Counter Value Registers 0-1
960x180TRCIDR8RO0x00000040ID Register 8-13
970x184TRCIDR9RO0x00000040
980x188TRCIDR10RO0x00000040
990x18CTRCIDR11RO0x00000011
1000x190TRCIDR12RO0x00000020
1010x194TRCIDR13RO0x00000000
112 0x1C0 TRCIMSPEC0RW0x00000000Implementation Specific Register 0
120 0x1E0 TRCIDR0RO0xXX001EFFID Register 0
121 0x1E4 TRCIDR1RO0x4100F401ID Register 1
122 0x1E8 TRCIDR2RO0x00420084ID Register 2
1230x1EC TRCIDR3RO0xXX090004ID Register 3
1240x1F0 TRCIDR4RO0x01270124ID Register 4
1250x1F4 TRCIDR5RO0x28C70840ID Register 5
130-140

0x208-0x240

TRCRSCTLRnRW-Resource Selection Registers 2-16
160-1610x280-0x284TRCSSCCRnRW-Single-Shot Comparator Control Registers 0-1
168-1690x2A0-0x2A4TRCSSCSRnRW-Single-Shot Comparator Status Registers 0-1
192 0x300TRCOSLARWO-OS Lock Access Register
193 0x304TRCOSLSRRO-OS Lock Status Register
1960x310TRCPDCRRW0x00000000Power Down Control Register
1970x314TRCPDSRRO0x00000023Power Down Status Register
256-2710x400-0x43CTRCACVRnRW-Address Comparator Value Registers 0-7
288-3030x480-0x4BCTRCACATRnRW-Address Comparator Access Type Registers 0-7
320-3210x500-0x504TRCDVCVRnRW-Data Value Comparator Value Registers 0-1
352-359 0x580-0x59CTRCDVCMRnRW-Data Value Comparator Mask Registers 0-1
3840x600TRCCIDCVR0RW-Context ID Comparator Value Register 0
9510xEDCTRCITMISCOUTRRW-Integration Miscellaneous Outputs Register
9520xEE0TRCITMISCINRRO-Integration Miscellaneous Inputs Register
9530xEE4TRCITATBIDRRW-Integration ATB Identification Register
9540xEE8TRCIRDDATARRW-Integration Data ATB Data Register
9550xEECTRCITIDATARRW-Integration Instruction ATB Data Register
9560xEF0TRCITDATBINRRO-Integration Data ATB In Register
9570xEF4TRCITIATBINRRO-Integration Instruction ATB In Register
9580xEF8TRCITDATBOUTRRW-Integration Data ATB Out Register
9590xEFCTRCITIATBOUTRRW-Integration Instruction ATB Out Register
960 0xF00 TRCITCTRLRW0x00000000Integration Mode Control Register
1000 0xFA0 TRCCLAIMSETRW0x00000000Claim Tag Set Register
1001 0xFA4 TRCCLAIMCLRRW0x00000000Claim Tag Clear Register
10020xFA8 TRCDEVAFF0RO-Device Affinity Register
1004 0xFB0 TRCLARWO-Software Lock Access Register
1005 0xFB4 TRCLSRRO-Software Lock Status Register
1006 0xFB8 TRCAUTHSTATUS RO-Authentication Status Register
1007 0xFBC TRCDEVARCHRO0x47704A17Device Architecture Register
1010 0xFC8 TRCDEVIDRO0x00000000Device ID Register
1011 0xFCC TRCDEVTYPERO0x00000013Device Type Register
1012-1019

0xFD0-0xFEC

TRCPIDRnRO-Peripheral Identification Registers
1020-1023

0xFF0-0xFFC

TRCCIDRnRO-Component Identification Registers

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