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A.2. Clocks and resets

Table A.2 shows the clock and reset signals.

Table A.2. Clock and reset signals
Signal nameTypeSource/destinationDescription
CLKInputClock sourceThis is the clock for the ETM-R7.
nRESETInput 

Debug reset. Resets programmers model as specified in the Embedded Trace Macrocell Architecture Specification ETMv4.


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