The SRAM Interface is for the memory access. This interface is only present in ETB and ETF configurations. Table A.5 shows the SRAM signals.
|Chip enable, active LOW.|
|Write enable, active LOW.|
|Write data. The data is valid in the same cycle as the address.|
|Read data. The data is returned one cycle after the address.|
[a] The width of this bus depends on the memory size and width.
[b] The width is dependent on the configured ATB width: