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A.5. AXI signals

This interface is present only in ETR configurations. For more information, see the AMBA 3 AXI Protocol Specification.

Table A.6. AXI signals

Signal

Type

Source

Description

AWADDRM[39:0]

Output

Master

Write address. The write address bus gives the address of the first transfer in a write bursttransaction.

AWLENM[3:0]

Output

Master

Burst length. The burst length gives the exact number of transfers in a burst.

AWSIZEM[2:0]

Output

Master

Burst size. This signal indicates the size of each transfer in the burst.

AWBURSTM[1:0]

Output

Master

Burst type. The burst type, coupled with the size information, describes how the address for each transfer within the burst is calculated.

AWLOCKM[1:0]

Output

Master

Lock type. This signal provides additional information about the atomic characteristicsof the transfer.

AWCACHEM[3:0]

Output

Master

Cache type. This signal indicates the bufferable, cacheable, write-through, write-back,and allocate attributes of the transaction.

AWPROTM[2:0]

Output

Master

Protection type. This signal indicates the normal, privileged, or secure protection levelof the transaction and whether the transaction is a data access or an instruction access.

AWVALIDM

Output

Master

Write address valid. This signal indicates that valid write address and controlinformation are available.

AWREADYM

Input

Slave

Write address ready. This signal indicates that the slave is ready to accept an address andassociated control signals.

WDATAM[a]

Output

Master

Write data. The write data bus can be 32, 64, or 128 bits wide.

WSTRBM[b]

Output

Master

Write strobes. This signal indicates which byte lanes to update in memory.

WLASTM

Output

Master

Write last. This signal indicates the last transfer in a write burst.

WVALIDM

Output

Master

Write valid. This signal indicates that valid write data and strobes are available.

WREADYM

Input

Slave

Write ready. This signal indicates that the slave can accept the write data.

BRESPM[1:0]

Input

Slave

Write response. This signal indicates the status of the write transaction. The permittedresponses are OKAY, EXOKAY, SLVERR, and DECERR.

BVALIDM

Input

Slave

Write response valid. This signal indicates that a valid write response is available.

BREADYM

Output

Master

Response ready. This signal indicates that the master can accept the response information.

ARADDRM[39:0]

Output

Master

Read address. The read address bus gives the initial address of a read burst transaction.

ARLENM[3:0]

Output

Master

Burst length. The burst length gives the exact number of transfers in a burst.

ARSIZEM[2:0]

Output

Master

Burst size. This signal indicates the size of each transfer in the burst.

ARBURSTM[1:0]

Output

Master

Burst type. The burst type, coupled with the size information, describes how the address for each transfer within the burst is calculated.

ARLOCKM[1:0]

Output

Master

Lock type. This signal provides additional information about the atomic characteristicsof the transfer.

ARCACHEM[3:0]

Output

Master

Cache type. This signal provides additional information about the cacheablecharacteristics of the transfer.

ARPROTM[2:0]

Output

Master

Protection type. This signal provides protection unit information for the transaction.

ARVALIDM

Output

Master

Read address valid. This signal indicates, when HIGH, that the read address and controlinformation is valid and remains stable until the address acknowledge signal, ARREADY, is high.

ARREADYM

Input

Slave

Read address ready. This signal indicates that the slave is ready to accept an address andassociated control signals.

RDATAM[a]

Input

Slave

Read data. The read data bus can be 32, 64, or 128 bits wide.

RRESPM[1:0]

Input

Slave

Read response. This signal indicates the status of the read transfer. The permitted responses are OKAY, EXOKAY, SLVERR, and DECERR.

RLASTM

Input

Slave

Read last. This signal indicates the last transfer in a read burst.

RVALIDM

Input

Slave

Read valid. This signal indicates that the required read data is available and the readtransfer can complete.

RREADYM

Output

Master

Read ready. This signal indicates that the master can accept the read data and responseinformation.

[a] The width is dependent on the configured AXI width:

[31:0]

32-bit AXI

[63:0]

64-bit AXI

[127:0]

128-bit AXI

[b] The width is dependent on the configured AXI width:

[3:0]

32-bit AXI

[7:0]

64-bit AXI

[15:0]

128-bit AXI


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