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2.2.2. Standard usage models for the TMC

This section describes the recommended usage model for the TMC in the following operating modes:

Circular Buffer mode

The recommended standard usage model in this mode is as follows:

  1. Wait until TMCReady is equal to one.

  2. Program the MODE Register for Circular Buffer mode.

  3. Program the FFCR Register. ARM recommends that you set the TrigOnTrigIn, FOnTrigEvt, StopOnFl, EnTI, and EnFt bits. This enables formatting, inserting a trigger when a trigger is observed on TRIGIN, and following a delay corresponding to the value of the TRG Register, flushing and then stopping the TMC.

  4. Program the TRG Register, to control the amount of buffer to be dedicated to the period after a trigger is observed.

  5. Set the TraceCaptEn bit in the CTL Register. This starts the trace session.

  6. Wait until TMCReady is equal to one. This indicates that the trace session is over.

  7. Read the contents of the trace buffer by performing successive reads to the RRD Register, until the value 0xFFFFFFFF is returned.

  8. Clear the TraceCaptEn bit in the CTL Register.

Software FIFO mode

The recommended standard usage model in this mode is as follows:

  1. Wait until TMCReady is equal to one.

  2. Program the MODE Register for Software FIFO mode.

  3. Program the BUFWM Register to the required threshold fill level. You can usually set this register to zero.

  4. Set the TraceCaptEn bit in the CTL Register. This starts the trace session.

  5. Start reading data from the RRD Register. If the value 0xFFFFFFFF is returned, then no data is available, and the read must be retried. Continue until the trace session is over, for example, following receipt of a trigger in the trace stream.

  6. Set the StopOnFl bit in the FFCR Register.

  7. Set the FlushMan bit in the FFCR Register. This flushes, then stops the TMC.

  8. Read data from the FIFO to get flushed data, retrying when 0xFFFFFFFF is returned, until TMCReady is equal to one. This indicates that all data has been written to the FIFO.

    Repeat {	Read Data from RRD register	If (Data = 0xFFFFFFFF) {		Read TMCReady from STS register		If (TMCReady = 1) {			Stop		}	}	Else {		Add Data to the end of the trace	}			}

  9. Read the remaining data from the FIFO, stopping when 0xFFFFFFFF is returned. This indicates that the FIFO is empty.

  10. Clear the TraceCaptEn bit in the CTL Register.

Hardware FIFO mode

The recommended standard usage model in this mode is as follows:

  1. Wait until TMCReady is equal to one.

  2. Program the MODE Register for Hardware FIFO mode.

  3. Program the FFCR Register, setting the EnFT and EnTI bits. It is not usually necessary to set any other bits in this mode, because the trace sink performs flush and stop control.

  4. Program the BUFWM Register to the required threshold fill level. You can usually set this register to zero.

  5. Set the TraceCaptEn bit in the CTL Register.

  6. The TMC is now operating in Hardware FIFO mode. Wait until the trace session is over, for example because the trace sink has stopped.

  7. Set the StopOnFl bit in the FFCR Register.

  8. Set the FlushMan bit in the FFCR Register. This flushes, then stops the TMC.

  9. Wait until TMCReady is equal to one. The TMC is now empty.

  10. Clear the TraceCaptEn bit in the CTL Register.

Detecting the end of trace data when formatting is disabled

The formatting protocol ensures that a continuous stream of 1s never occurs in a formatted trace stream. When formatting is enabled, that is EnFt bit in the FFCR register is set, and the trace memory is empty, the TMC returns 0xFFFFFFFF for RRD reads to indirectly indicate that there is no valid trace data to read.

However, when formatting is disabled, that is, the EnFt bit in the FFCR Register is cleared, it is possible that a continuous stream of 1s appears in the non-formatted trace stream. In this case, you must combine the standard use cases that Standard usage models for the TMC lists with the following techniques:

  • The CBUFLEVEL Register indicates the current fill level of the trace buffer, and is valid when TraceCaptEn is equal to one, and when scatter-gather operation is disabled. You can use the value returned by this register to ensure that the RRD is read-only when trace memory has valid data.

  • In scatter-gather operation, the CBUFLEVEL Register is not valid. However, the Empty bit in the STS Register is valid while TraceCaptEn is equal to one. You can use the Empty bit to ensure that the RRD is read-only when trace memory has valid data.

Note

This requires a read of the STS Register before every RRD read.

In practice, because of the low overhead of the formatter, 6%, it is expected that most usage models enable the formatter at all times.

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