You copied the Doc URL to your clipboard.

2.2.1. TMC architectural state machine

The TMC has an architectural state machine. Figure 2.4 shows the transactions of the state machine. The states are defined mainly by the Trace Capture Enable bit in the CTL Register, and the TMCReady bit in the STS Register.

Figure 2.4. TMC architectural state machine

Figure 2.4. TMC architectural state machine

The following sections describe the states:


This state is entered after reset, and, ultimately, whenever TraceCaptEn is cleared. You must perform all programming in this state.

In this state, the contents of most registers, including the MODE and FFCR registers, have no effect.

For backwards-compatibility, the contents of the circular buffer can be read in this state, provided that it was captured with scatter-gather disabled. You must manage the read pointer manually. This usage is deprecated in favor of reading the contents of the Circular Buffer while in the Stopped state instead.

The Running state is entered from this state by setting TraceCaptEn.


This is the functional state during which trace capture is performed.

The Stopping state is entered from this state when a Stop Event occurs. The Stop events are:

  • a flush caused by any reason other than a request on AFVALIDM completes, and the StopOnFl bit in the FFCR is set

  • a Trigger Event occurs, and the StopOnTrigEvt bit in the FFCR is set.


In this state, the TMC begins to drain its contents. From the programmer’s model, this state is indistinguishable from the Running state.

The Stopped state is entered from this state when:

  • A Stop sequence has been written to the end of the trace. See Standard usage models for the TMC.

  • The formatter and write buffer are empty.

  • In Hardware FIFO mode, the FIFO and unformatter are empty.


In Software FIFO mode, it might be necessary to read additional data from the FIFO to make space for the remaining data, such as the Stop sequence, to be written to it. If no such reads are performed, the Stopped state might never be reached.


In this state, no more trace capture takes place, but data still in the TMC can be read out. When in this state:

  • In Circular Buffer mode, the contents of the captured buffer can be read out over APB.

  • In Circular Buffer mode, a drain can be initiated by setting the DrainBuffer bit in the FFCR. See Draining.

  • In Software FIFO mode, the remaining contents of the FIFO can be read out over APB.

The Disabled state is entered from this state by clearing the TraceCaptEn bit.


In this state, the contents of the buffer captured in Circular Buffer mode are drained over the ATB interface. The TMC returns to the Stopped state as soon as the buffer is empty.


This is an emergency stop state that can be entered at any time by clearing the TraceCaptEn bit. It differs from the Stopping state as follows:

  • The TMC does not attempt to empty the contents of the FIFO in Hardware FIFO mode. Trace not yet output on the ATB master interface is lost.

  • The next transition is to the Disabled state rather than the Stopped state. This means that:

    • in Circular Buffer mode, a drain operation is not possible, and the buffer contents are lost if they were captured with scatter-gather operation enabled

    • in Software FIFO mode, trace not yet retrieved is lost.

  • Exit from this state is not dependent on reads being performed from the RRD Register, in Software FIFO mode, or writes on the ATB master interface being accepted in Hardware FIFO mode. If the FIFO is full, existing data is overwritten to enable the Stop sequence to complete.

In an ETR configuration, transition to the Disabled state can still be delayed indefinitely if the AXI master interface stalls indefinitely. In this case, it is necessary to clear the source of the stall because it is not possible to abort an active AXI transaction.

Was this page helpful? Yes No