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This glossary describes some of the terms used in technical documents from ARM.

Advanced eXtensible Interface (AXI)

A bus protocol that supports separate phases for address or control and data, unaligned data transfers using byte strobes, burst-based transactions with only start address issued, separate read and write data channels, issuing multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to provide timing closure.

The AXI protocol includes optional extensions for signaling for low-power operation.

Advanced Microcontroller Bus Architecture (AMBA)

The AMBA family of protocol specifications is the ARM open standard for on-chip buses. AMBA provides a strategy for the interconnection and management of the functional blocks that make up a System-on-Chip (SoC). Applications include the development of embedded systems with one or more processors or signal processors and multiple peripherals. AMBA defines a common backbone for SoC modules, and therefore complements a reusable design methodology.

Advanced Peripheral Bus (APB)

A bus protocol that is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. It connects to the main system bus through a system-to-peripheral bus bridge that helps reduce system power consumption.

Advanced Trace Bus (ATB)

A bus used by trace devices to share CoreSight capture resources.


A data item stored at an address that is divisible by the number of bytes that defines its data size is said to be aligned. Aligned doublewords, words, and halfwords have addresses that are divisible by eight, four, and two respectively. The terms doubleword-aligned, word-aligned, and halfword-aligned therefore stipulate addresses that are divisible by eight, four, and two respectively. An aligned access is one where the address of the access is aligned to the size of an element of the access.


See Advanced Microcontroller Bus Architecture.


See Advanced Peripheral Bus.


See Advanced Trace Bus.


See Advanced eXtensible Interface.

AXI channels, channel order and interfaces

The block diagram shows:

  • the order in which AXI channel signals are described

  • the master and slave interface conventions for AXI components.

AXI signal names have a one or two letter prefix that denotes the AXI channel as follows:


Write address channel.


Write data channel.


Write response channel.


Read address channel.


Read data channel.

General descriptions of AXI signals use x to represent this prefix, for example, xVALID and xREADY.


Alternative word for an individual transfer within a burst. For example, an INCR4 burst comprises four beats.

See Also Burst.


A group of transfers to consecutive addresses. Because the addresses are consecutive, the device transmitting the data does not have to supply an address for any transfer after the first one. This increases the speed at which the burst occurs. If using an AMBA interface, the transmitting device controls the burst using signals that indicate the length of the burst and how the addresses are incremented.

See Also Beat.


ARM on-chip debug and trace components, that provide the infrastructure for monitoring, tracing, and debugging a complete system on chip.

See Also CoreSight ECT, CoreSight ETB, CoreSight ETM, Trace Funnel, and Trace Port Interface Unit (TPIU).

CoreSight ETB

CoreSight ETB is a trace sink that provides on-chip storage of trace data using a configurable sized RAM.

See Also CoreSight, CoreSight ETB, Embedded Trace Buffer, and Embedded Trace Macrocell.

Cross Trigger Interface (CTI)

Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.


See Cross Trigger Interface.


See Debug Access Port.

Debug Access Port (DAP)

A block that acts as a master on a system bus and provides access to the bus from an external debugger.


A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

Embedded Trace Buffer (ETB)

Provides on-chip storage of trace data using a configurable sized RAM.

Embedded Trace Macrocell (ETM)

A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.


See Embedded Trace Buffer.


See Embedded Trace Macrocell.


In an ETB or TPIU, an internal input block that embeds the trace source ID in the data to create a single trace stream.


A computer that provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.

JTAG Access Port (JTAG-AP)

An optional component of the DAP that provides debugger access to on-chip scan chains.


A complex logic block with a defined interface and behavior. A typical VLSI system comprises several macrocells, such as a processor, an ETM, and a memory block integrated with application-specific logic.


See Physical Address.

Physical Address (PA)

The address that identifies a main memory location.

Prefetch abort

An indication from a memory system to the processor that an instruction has been fetched from an illegal memory location. An exception must be taken if the processor attempts to execute the instruction. A Prefetch abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction memory.

See Also Data abort, External abort and Abort.


Memory operations that have the semantics of a load. See the ARM Architecture Reference Manual for more information.


In an ARM trace macrocell, a replicator enables two trace sinks to be wired together and to operate independently on the same incoming trace stream. The input trace stream is output onto two independent ATB ports.


Registers and instructions that are reserved are Unpredictable unless otherwise stated. Bit positions described as Reserved are UNK/SBZP.


See Should Be Zero.


See Should Be Zero or Preserved.

Serial Wire Debug (SWD)

A debug implementation that uses a serial connection between the SoC and a debugger.

This connection normally requires a bi-directional data signal and a separate clock signal, rather than the four to six signals required for a JTAG connection.

Serial Wire Debug Port (SWDP)

The interface for Serial Wire Debug.

Should Be Zero (SBZ)

Software must write as 0, or all 0s for bit fields. Writing any other value produces Unpredictable results.

Should Be Zero or Preserved (SBZP)

Software must write as 0, or all 0s for a bit field, if the value is being written without having previously been read, or if the register has not been initialized. If the register has previously been read, software must preserve the field value by writing back the value that was read from the same field on the same processor.


See Serial Wire Debug.


See Serial Wire Debug Port.


See Trace Port Analyzer.


See Trace Port Interface Unit.

Trace funnel

In CoreSight, a device that combines multiple trace sources onto a single bus.

See Also CoreSight and Embedded Trace Macrocell.

Trace port

A port on a device, such as a processor or ASIC, used to output trace information.

Trace Port Analyzer (TPA)

A hardware device that captures trace information output on a trace port. This can be a low-cost product designed specifically for trace acquisition, or a logic analyzer.

Trace Port Interface Unit (TPIU)

Drains trace data and acts as a bridge between the on-chip trace data and the data stream captured by a TPA.


An Unknown value does not contain valid data, and can vary from moment to moment, instruction to instruction, and implementation to implementation. An Unknown value must not be a security hole.


See Unpredictable.


For a processor means the behavior cannot be relied on. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system.


A 32-bit data item. Words are normally word-aligned in ARM systems.


Operations that have the semantics of a store. See the ARM Architecture Reference Manual for more information.

Write buffer

A block of high-speed memory implemented to optimize stores to main memory.

Write interleave capability

The number of data-active write transactions for which the interface can transmit data. This is counted from the earliest transaction.

Write interleave depth

The number of data-active write transactions for which the interface can receive data.

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