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3.3.34. Lock Access Register

The LAR Register characteristics are:


Enables write access to device registers.

External accesses from a debugger, PADDRDBG31 = 1, are not subject to the Lock registers. A debugger does not have to unlock the component to write and modify the registers in the component.


Present in all configurations.

Figure 3.34 shows the LAR Register bit assignments.

Figure 3.34. LAR Register bit assignments

Figure 3.34. LAR Register bit assignments

Table 3.35 shows the LAR Register bit assignments.

Table 3.35. LAR Register bit assignments

A write of 0xC5ACCE55 enables additional write access to this device. A write of any value other than 0xC5ACCE55 can have the affect of removing write access.

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