The PSCR Register characteristics are:
Determines the reload value of the Periodic Synchronization Counter. This enables the frequency of synchronization information to be optimized to the trace capture buffer size.
This counter is enabled only when the TraceCaptEn bit in the Control Register, CTL,
0x020, is set. Writing to this register, other than when in Disabled state, results in Unpredictable behavior.
Present in all configurations.
Figure 3.20 shows the PSCR Register bit assignments.
Table 3.21 shows the PSCR Register bit assignments.
Determines the reload value of the Synchronization
Counter. The reload value takes effect the next time the counter
reaches zero. Reads from this register return the reload value programmed
into this register. This register is set to