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3.3.2. Status Register

The STS Register characteristics are:


TMC Status register.


Present in all configuration.

Figure 3.2 shows the STS Register bit assignments.

Figure 3.2. STS Register bit assignments

Figure 3.2. STS Register bit assignments

Table 3.3 shows the STS Register bit assignments.

Table 3.3. STS Register bit assignments



This bit indicates that an error has occurred on the AXI master interface. The error could be because of an error response from an AXI slave or because of the status of the Authentication interface inputs:

  • This bit is set whenever an AXI read or write response of type SLVERR (b10) or DECERR (b11) is encountered. These error types are not distinguished between, and EXOKAY (b01) is treated as OKAY (b00). An exclusive okay response is illegal because the TMC does not request any exclusive accesses.

  • This bit is also set instead of initiating an AXI access when Non-secure Invasive Debug is disabled, and instead of initiating a secure access when Secure Invasive Debug is disabled. For more information, see Authentication Status Register and AXI Control Register.

When the Memory Error Status bit is set:

  • No more AXI accesses are performed other than any commands in the internal pipeline.

  • Outstanding AXI read and write responses are ignored. Pending responses are counted, but the responses received are discarded.

  • A read access to the RRD Register or a write access to the RWD Register returns a slave error. This includes accesses to these registers that would otherwise have been ignored without returning a slave error, for example, when the TMC is enabled and in Circular Buffer mode or in Hardware Read FIFO mode.

  • The formatter stops, and sets TMCReady when it has stopped.

  • Reading the RWP, RWPHI, RRP, and RRPHI registers returns Unknown values.

This bit is cleared by:

  • writing to this register with this bit set when TMCReady is HIGH

  • setting TraceCaptEn when TraceCaptEn is LOW.


If set, this bit indicates that the TMC does not contain any valid trace data in the trace memory. This does not, however, mean that the pipeline stages within the TMC are empty. To determine whether the pipeline stages within the TMC are empty, read the TMCReady bit.

This bit is set on reset.

This bit is valid only when TraceCaptEn is HIGH. This bit reads as zero when TraceCaptEn is LOW.


In Circular Buffer mode, it is possible that the Empty bit and the Full bit in this register are one at the same time because the Full bit in this mode, when set, does not clear until TraceCaptEn is set.


This bit is set when trace capture has stopped, and all internal pipelines and buffers have drained. Unlike TMCReady, it is not affected by buffer drains and AXI accesses.The ACQCOMP output reflects the value of this bit unless the TMC is in integration mode.


This bit is set when all the following are true:

  • Trace capture has stopped and all internal pipelines and buffers have drained. This is equivalent to being in the Stopped or Disabled state. See TMC architectural state machine.

  • The TMC is not training because of the DrainBuffer bit of the FFCR being set.

  • In ETR configuration, the AXI interface is not busy. This case can be used to detect page table reads in scatter-gather mode when in Stopped state.


The Triggered bit is set when trace capture is in progress and the TMC has detected a Trigger Event. For more information, see Trigger, flush and stop events.

This bit is cleared when leaving Disabled state.

This bit is operational only in the Circular Buffer mode. In all other modes, this bit is always LOW.

This bit does not indicate that a trigger has been embedded in the formatted output trace data from the TMC. Trigger indication on the output trace stream is determined by the programming of the Formatter and Flush Control Register, FFCR, 0x304.


This bit can help to determine how much of the trace buffer contains valid data.

Circular Buffer mode

This flag is set when the RAM write pointer wraps around the top of the buffer, and remains set until the TraceCaptEn bit is cleared and set.

Software FIFO mode and Hardware FIFO mode

This flag indicates that the current space in the trace memory is less than or equal to the value programmed in the BUFWM Register, that is, Fill level >= MEM_SIZE - BUFWM. In the ETR configuration, if the TMC is programmed for scatter-gather operation, this bit indicates whether the Trace memory is currently full regardless of the value programmed in the BUFWM Register.


In scatter-gather mode, the TMC might be unable to accept new trace without this bit being set, if a read from the scatter-gather tables is delayed sufficiently.

When entering Disabled state, this bit retains its previous value. When exiting Disabled state, this bit is cleared.

The FULL output from the TMC reflects the value of this register bit, except when the Integration Mode bit in the ITCTRL Register, 0xF00, is set.

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