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A.10. Test interface signals

Table A.11 shows the test interface signals.

Table A.11. Test interface signals




DFTTESTMODEInputTest mode. This signal is used to force the STM clock on in test mode.
DFTCLKDISABLEInputTest clock disable. This signal is used to switch off the STM clock in the capture phase of DFT testing of other components in the system.

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