You copied the Doc URL to your clipboard.
Table A.11 shows the test interface signals.
Signal | Type | Description |
|---|---|---|
| DFTTESTMODE | Input | Test mode. This signal is used to force the STM clock on in test mode. |
| DFTCLKDISABLE | Input | Test clock disable. This signal is used to switch off the STM clock in the capture phase of DFT testing of other components in the system. |