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A.5. AXI signals

This interface is present only in ETR configurations. For more information, see the AMBA 3 AXI Protocol Specification. Table A.6 shows the AXI signals.

Table A.6. AXI signals

Signal

Type

Source

Description

AWADDRM[39:0]

Output

Master

Write address.

AWLENM[3:0]

Output

Master

Burst length.

AWSIZEM[2:0]

Output

Master

Burst size.

AWBURSTM[1:0]

Output

Master

Burst type.

AWLOCKM[1:0]

Output

Master

Lock type.

AWCACHEM[3:0]

Output

Master

Cache type.

AWPROTM[2:0]

Output

Master

Protection type.

AWVALIDM

Output

Master

Write address valid.

AWREADYM

Input

Slave

Write address ready.

WDATAM[a]

Output

Master

Write data.

WSTRBM[b]

Output

Master

Write strobes.

WLASTM

Output

Master

Write last.

WVALIDM

Output

Master

Write valid.

WREADYM

Input

Slave

Write ready.

BRESPM[1:0]

Input

Slave

Write response.

BVALIDM

Input

Slave

Write response valid.

BREADYM

Output

Master

Response ready.

ARADDRM[39:0]

Output

Master

Read address.

ARLENM[3:0]

Output

Master

Burst length.

ARSIZEM[2:0]

Output

Master

Burst size.

ARBURSTM[1:0]

Output

Master

Burst type.

ARLOCKM[1:0]

Output

Master

Lock type.

ARCACHEM[3:0]

Output

Master

Cache type.

ARPROTM[2:0]

Output

Master

Protection type.

ARVALIDM

Output

Master

Read address valid.

ARREADYM

Input

Slave

Read address ready.

RDATAM[a]

Input

Slave

Read data.

RRESPM[1:0]

Input

Slave

Read response.

RLASTM

Input

Slave

Read last.

RVALIDM

Input

Slave

Read valid.

RREADYM

Output

Master

Read ready.

[a] The width is dependent on the configured AXI width:

[31:0]

32-bit AXI

[63:0]

64-bit AXI

[127:0]

128-bit AXI

[b] The width is dependent on the configured AXI width:

[3:0]

32-bit AXI

[7:0]

64-bit AXI

[15:0]

128-bit AXI


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