The STS Register characteristics are:
TMC Status register.
Present in all configuration.
Figure 3.2 shows the STS Register bit assignments.
Table 3.3 shows the STS Register bit assignments.
This bit indicates that an error has occurred on the AXI master interface. The error could be because of an error response from an AXI slave or because of the status of the Authentication interface inputs:
When the Memory Error Status bit is set:
This bit is cleared by:
If set, this bit indicates that the TMC does not contain any valid trace data in the trace memory. This does not, however, mean that the pipeline stages within the TMC are empty. To determine whether the pipeline stages within the TMC are empty, read the TMCReady bit.
This bit is set on reset.
This bit is valid only when TraceCaptEn is HIGH. This bit reads as zero when TraceCaptEn is LOW.
In Circular Buffer mode, it is possible that the Empty bit and the Full bit in this register are one at the same time because the Full bit in this mode, when set, does not clear until TraceCaptEn is set.
This bit is set when trace capture has stopped, and all internal pipelines and buffers have drained. Unlike TMCReady, it is not affected by buffer drains and AXI accesses.The ACQCOMP output reflects the value of this bit unless the TMC is in integration mode.
This bit is set when all the following are true:
The Triggered bit is set when trace capture is in progress and the TMC has detected a Trigger Event. For more information, see Trigger, flush and stop events.
This bit is cleared when leaving Disabled state.
This bit is operational only in the Circular Buffer mode. In all other modes, this bit is always LOW.
This bit does not indicate that
a trigger has been embedded in the formatted output trace data from
the TMC. Trigger indication on the output trace stream is determined
by the programming of the Formatter and Flush Control Register,
This bit can help to determine how much of the trace buffer contains valid data.
When entering Disabled state, this bit retains its previous value. When exiting Disabled state, this bit is cleared.
The FULL output from the TMC reflects the
value of this register bit, except when the Integration Mode bit in
the ITCTRL Register,