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A.4. SRAM signals

The SRAM Interface is for the memory access. This interface is only present in ETB and ETF configurations. Table A.5 shows the SRAM signals.

Table A.5. SRAM signals

Signal

Type

Description

MEMCEN

Output

Chip enable, active LOW.

MEMADDR[a]

Output

Address.

MEMWEN

Output

Write enable, active LOW.

MEMD[b]

Input

Write data. The data is valid in the same cycle as the address.

MEMQ[b]

Output

Read data. The data is returned one cycle after the address.

[a] The width of this bus depends on the memory size and width.

[b] The width is dependent on the configured ATB width:

[63:0]

32-bit ATB

[127:0]

64-bit ATB

[255:0]

128-bit ATB


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