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3.3.15. AXI Control Register

The AXICTL Register characteristics are:

Purpose

Controls TMC accesses to system memory through the AXI master interface.

The TMC performs only Data accesses, so ARPROTM[2] and AWPROTM[2] outputs are LOW for all AXI accesses.

Writing to this register when not in Disabled state results in Unpredictable behavior. In most cases, you can set bits [5:0] of this register to b111111.

Configurations

Present in ETR configurations only.

Figure 3.15 shows the AXICTL Register bit assignments.

Figure 3.15. AXICTL Register bit assignments

Figure 3.15. AXICTL Register bit assignments

Table 3.16 shows the AXICTL Register bit assignments.

Table 3.16. AXICTL Register bit assignments
BitsNameFunction
[31:12]Reserved

Reserved.

[11:8]WrBurstLen

This field indicates the maximum number of data transfers that can occur within each burst initiated by the TMC on the AXI master interface. The Write burst initiated on the AXI can be of a smaller length that the programmed value in the case when the formatter has stopped because of a stop condition having occurred. Programming this field to a burst length value greater than the write buffer depth results in a burst length that is equal to the write buffer depth.

The burst length programmed must be compatible with the trace buffer size and the AXI data width so that the total number of bytes of data transferred in a burst is not greater than the trace buffer size or, if scatter-gather operation is enabled, is not greater than 4KB. Programming an incompatible burst length results in Unpredictable behavior.

It is recommended that this value be set to no more than half the write buffer depth. Also, it is recommended that this value be set to enable an AXI burst of at least one frame of trace data.

This field is decoded as follows:

0x0

One data transfer per burst. This is the default.

0x1

Maximum of two data transfers per burst.

...

0xF

Maximum of 16 data transfers per burst.

[7]ScatterGatherMode

This bit indicates whether trace memory is accessed as a single buffer in system memory or as a linked-list based scatter-gather memory. This bit is ignored when in Disabled state.

0

Trace memory is a single contiguous block of system memory.

1

Trace memory is spread over multiple blocks of system memory based on a linked-list mechanism. For more information, see Scatter-gather.

[6]ReservedReserved.
[5]CacheCtrlBit3

This bit controls the value driven on the ARCACHEM[3] or AWCACHEM[3] signal on the AXI master interface when performing AXI transfers. If CacheCtrlBit1 is LOW, this bit must also be LOW to comply with the AXI protocol. Setting this bit to HIGH when the CacheCtrlBit1 is LOW results in Unpredictable behavior.

0

Do not cache allocate on writes.

1

Cache allocate on writes.

[4]CacheCtrlBit2

This bit controls the value driven on the ARCACHEM[2] or AWCACHEM[2] signal on the AXI master interface when performing AXI transfers. If CacheCtrlBit1 is LOW, this bit must also be LOW to comply with the AXI protocol. Setting this bit to HIGH when the CacheCtrlBit1 is LOW results in Unpredictable behavior.

0

Do not cache allocate on reads.

1

Cache allocate on reads.

[3]CacheCtrlBit1

This bit controls the value driven on the ARCACHEM[1] or AWCACHEM[1] signal on the AXI master interface when performing AXI transfers.

0

Non-cacheable.

1

Cacheable.

[2]CacheCtrlBit0

This bit controls the value driven on the ARCACHEM[0] or AWCACHEM[0] signal on the AXI master interface when performing AXI transfers.

0

Non-bufferable.

1

Bufferable.

[1]ProtCtrlBit1

This bit controls the value driven on ARPROTM[1] or AWPROTM[1] on the AXI master interface when performing AXI transfers.

0

Secure access.

1

Non-secure access.

[0]ProtCtrlBit0

This bit controls the value driven on ARPROTM[0] or AWPROTM[0] on the AXI master interface when performing AXI transfers.

0

Normal access.

1

Privileged access. A privileged processing mode might have a greater level of access within a system.


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