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3.3.19. Formatter and Flush Control Register

The FFCR Register characteristics are:

Purpose

Controls the generation of the stop, trigger, and flush events.

Multiple flush generating conditions can be enabled together. However, if a second or third flush event is generated, then the current flush completes before the next flush is serviced.

Multiple trigger indication conditions can be enabled simultaneously, which can cause the appearance of multiple triggers in the trace stream.

Note

To perform a stop on flush completion through a manually-generated flush request, two write operations to the register are required:

  • one to enable the stop event, if it is not already enabled

  • one to generate the manual flush.

Configurations

Present in all configurations.

Figure 3.19 shows the FFCR Register bit assignments.

Figure 3.19. FFCR Register bit assignments

Figure 3.19. FFCR Register bit assignments

Table 3.20 shows the FFCR Register bit assignments.

Table 3.20. FFCR Register bit assignments
BitsNameFunction
[31:15]Reserved

Reserved.

[14]DrainBuffer

In ETF configuration, this bit is used to enable draining of the trace data through the ATB master interface after the formatter has stopped. This is useful in Circular Buffer mode to capture trace data into trace memory and then to drain the captured trace through the ATB master interface.

Writing a one to this bit when in Stopped state starts the drain of the contents of the trace buffer through the ATB Master interface. This bit always reads as zero. The TMCReady bit, STS Register, 0x00C, goes LOW while the drain is in progress.

This bit is functional only when the TMC is in Circular Buffer mode and formatting is enabled, EnFt bit in FFCR Register is set. Setting this bit when the TMC is in any other mode, or when not in Stopped state, results in Unpredictable behavior.

When trace capture is complete in Circular Buffer mode, all of the captured trace must be retrieved from the trace memory through the same mechanism, either read all trace data out through RRD reads, or drain all trace data by setting the DrainBuffer bit. Setting the DrainBuffer bit after some of the captured trace has been read out through RRD results in Unpredictable behavior.

0

Trace data is not drained through ATB master interface.

1

Trace data is drained through ATB master interface.

[13]StopOnTrigEvt

If this bit is set, the formatter is stopped when a Trigger Event has been observed. For more information on Trigger Events, see Trigger, flush and stop events.

This bit is cleared on reset.

Enabling the TMC in Software FIFO mode, or Hardware FIFO mode, with this bit set results in Unpredictable behavior.

0

Trace capture is not stopped when a Trigger Event is observed.

1

Trace capture is stopped when a Trigger Event is observed.

[12]StopOnFl

If this bit is set, the formatter is stopped on completion of a flush operation.

For more information on Trigger Events, see Trigger, flush and stop events.

When the TMC is configured as an ETF, if a flush is initiated by the ATB master interface, its completion does not lead to a formatter stop regardless of the value programmed in this bit.

0

Trace capture is not stopped when FLUSH is completed.

1

Trace capture is stopped when FLUSH is completed.

[11]ReservedReserved.
[10]TrigOnFl

If this bit is set, a trigger is indicated on the trace stream when a flush completes. For more information, see Trigger, flush and stop events.

If EnFt and EnTI are both clear, this bit is ignored and no trigger is inserted into the trace stream.

When the TMC is configured as an ETF, if a flush is initiated by the ATB Master interface, its completion does not lead to a trigger indication on the trace stream regardless of the value programmed in this bit.

0

A trigger is not indicated on the trace stream when a flush completes.

1

A trigger is indicated on the trace stream when a flush completes.

[9]TrigOnTrigEvt

If this bit is set, a trigger is indicated on the output trace stream when a Trigger Event occurs. For more information, see Trigger, flush and stop events.

If EnFt and EnTI are both clear, this bit is ignored and no trigger is inserted into the trace stream.

This bit is not supported in Software FIFO mode or Hardware FIFO mode.

0

A trigger is not indicated on the trace stream when a Trigger Event occurs.

1

A trigger is indicated on the trace stream when a Trigger Event occurs.

[8]TrigOnTrigIn

If this bit is set, a trigger is indicated on the trace stream when a rising edge is detected on the TRIGIN input. For more information, see Trigger, flush and stop events.

If EnFt and EnTI are both clear, this bit is ignored and no trigger is inserted into the trace stream.

0

A trigger is not indicated on the trace stream when a rising edge is detected on the TRIGIN input.

1

A trigger is indicated on the trace stream when a rising edge is detected on the TRIGIN input.

[7]ReservedReserved.
[6]FlushMan

Manually generate a flush of the system. Setting this bit causes a flush to be generated.

If TraceCaptEn bit in CTL Register is 0, then writes to this bit are ignored.

This bit is cleared automatically when a flush completes. For more information, see Trigger, flush and stop events. This bit is clear on reset.

0

Manual Flush is not initiated.

1

Manual Flush is initiated.

[5]FOnTrigEvt

Setting this bit generates a flush when a Trigger Event occurs. If StopOnTrigEvt is set, this bit is ignored. For more information, see Trigger, flush and stop events.

This bit is clear on reset.

This bit is not supported in Software FIFO mode or Hardware FIFO mode.

0

Flush-on-trigger-event disabled.

1

Flush-on-trigger-event enabled.

[4]FOnFlIn

Setting this bit enables the detection of transitions on the FLUSHIN input by the TMC. If this bit is set and the Formatter has not already stopped, a rising edge on FLUSHIN initiates a flush request.

This bit is clear on reset.

0

Flush-on-FLUSHIN feature is disabled.

1

Flush-on-FLUSHIN feature is enabled.

[3:2]ReservedReserved
[1]EnTI

Setting this bit enables the insertion of triggers in the formatted trace stream. A trigger is indicated by inserting one byte of data 8'h00 with ATID 7'h7D in the trace stream. Trigger indication on the trace stream is additionally controlled by the register bits TrigOnFl, TrigOnTrigEvt, and TrigOnTrigIn in the FFCR Register, 0x304. This bit can only be changed when TMCReady is HIGH, and TraceCaptEn is LOW. This bit takes effect only when the EnFt register bit in this register is set. If EnTI bit is set to HIGH when EnFt is LOW, it results in formatting being enabled.

This bit is clear on reset.

0

Triggers are not embedded into the formatted trace stream.

1

Embed triggers into formatted trace stream.

[0]EnFt

If this bit is set, formatting is enabled. This bit is clear on reset. This bit is ignored when in Disabled state.

If this bit is clear, formatting is disabled. Incoming trace data is assumed to be from a single trace source. If multiple ATIDs are received by the TMC when trace capture is enabled and the formatter is disabled, it results in interleaving of trace data. Disabling of formatting is deprecated and is supported in the TMC for backwards-compatibility with earlier versions of the ETB. Disabling of formatting is supported only in Circular Buffer mode. Features in the TMC such as the FIFO modes and the DrainBuffer bit that are not part of the earlier versions of the ETB do not support disabling of formatting.

If EnTI bit is set to HIGH when EnFt is LOW, it results in formatting being enabled. If the TMC is enabled in a mode other than Circular Buffer mode with EnFt LOW, it results in formatting being enabled.

0

Formatting disabled.

1

Formatting enabled.


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