The LAR Register characteristics are:
Enables write access to device registers.
External accesses from a debugger, PADDRDBG31 = 1, are not subject to the Lock registers. A debugger does not have to unlock the component to write and modify the registers in the component.
Present in all configurations.
Figure 3.34 shows the LAR Register bit assignments.
Table 3.35 shows the LAR Register bit assignments.
A write of