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3.3.20. Periodic Synchronization Counter Register

The PSCR Register characteristics are:

Purpose

Determines the reload value of the Periodic Synchronization Counter. This enables the frequency of synchronization information to be optimized to the trace capture buffer size.

This counter is enabled only when the TraceCaptEn bit in the Control Register, CTL, 0x020, is set. Writing to this register, other than when in Disabled state, results in Unpredictable behavior.

Configurations

Present in all configurations.

Figure 3.20 shows the PSCR Register bit assignments.

Figure 3.20. PSCR Register bit assignments

Figure 3.20. PSCR Register bit assignments

Table 3.21 shows the PSCR Register bit assignments.

Table 3.21. PSCR Register bit assignments
BitsNameFunction
[31:5]Reserved

Reserved.

[4:0]PSCount

Determines the reload value of the Synchronization Counter. The reload value takes effect the next time the counter reaches zero. Reads from this register return the reload value programmed into this register. This register is set to 0xA on reset, corresponding to a synchronization period of 1024 bytes.

0x0

Synchronization disabled.

0x1-0x6

Reserved.

0x7-0x1B

Synchronization period is 2PSCount bytes. For example, a value of 0x7 gives a synchronization period of 128 bytes.

0x1C-0x1F

Reserved.


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