The RWP Register characteristics are:
The RWP Register sets the write pointer used to write entries into trace RAM.
Writing to this register other than when in Disabled state results in Unpredictable behavior. When in Disabled state, a write to this register sets the value of the trace memory address to which data is written on a subsequent RWD write.
The value written to this register must be a byte-address aligned to the width of the trace memory databus and to a frame boundary. For example, for 64-bit wide trace memory and 128-bit wide trace memory, the four LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must be 0s. The width of the trace memory can be obtained by reading the MEMWIDTH field in the DEVID Register,
Reading this register returns the current memory location being referenced, to which the next write would occur. When one complete buffer or FIFO entry has been written to the RWD Register, the RAM Write Pointer Register is incremented by the number of bytes per memory width of data. For example, for 64-bit wide memory, it is incremented by eight. For 128-bit wide memory it is incremented by 16 for every complete memory entry write.
When this register wraps around its maximum value, the Full flag in the Status Register, STS,
0x00C, is set.
In the ETB or ETF configurations, the width of this register is log2(MEM_SIZE*4). In the ETR configuration, this register is 32 bits wide, and the contents of this register represent the lower 32 bits of the 40-bit AXI address used to access trace memory.
In ETB and ETF configurations, when in Circular Buffer mode, this register can be used to set the address to start capturing data from. This is for backwards compatibility purposes, to enable the FULL signal to be generated before the buffer becomes full. In other configurations and modes, the RAM Write Pointer is reset to the start of trace memory when exiting Disabled state.This register can be read:
when in Disabled state
when in Stopped state, in Circular Buffer mode
when in Running, Stopping or Stopped states, in Software FIFO mode.
Present in all configurations.
Figure 3.5 shows the RWP Register bit assignments.
Table 3.6 shows the RWP Register bit assignments.