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3.3.6. Trigger Counter Register

The TRG Register characteristics are:

Purpose

In Circular Buffer mode, specifies the number of 32-bit words to capture in the Trace RAM following the detection of either a rising edge on the TRIGIN input or a trigger packet in the incoming trace stream, ATID = 7'h7D. On capturing the specified number of datawords, a Trigger Event occurs. The effect of a Trigger Event on TMC behavior is controlled by the FFCR Register, 0x304. See Trigger, flush and stop events.

The number of 32-bit words written into the Trace RAM following the trigger is the value stored in this register plus one. This register is ignored when the TMC is in Software FIFO mode or Hardware FIFO mode.

When the trigger counter starts counting, any additional triggers, either on TRIGIN or in the incoming trace stream, are ignored until the counter reaches zero. When the trigger counter has reached zero, it remains at zero until it is re-programmed with a write to this register.

This register is cleared when TMCReady goes HIGH, so that the state of the counter when trace capture has stopped does not affect a subsequent trace capture session.

Writing to this register when not in Disabled state results in Unpredictable behavior.

A read access to this register is permitted at any time when in Disabled state, or in Circular Buffer mode. A read access returns the current value of the Trigger counter.

The width of this register and the Trigger counter depends on the size of the trace memory. In ETB and ETF configurations, the width of the counter is log2(MEMSIZE). The width of this register in ETR configuration is 32 bits.

Configurations

Present in all configurations.

Figure 3.6 shows the TRG Register bit assignments.

Figure 3.6. TRG Register bit assignments

Figure 3.6. TRG Register bit assignments

Table 3.7 shows the TRG Register bit assignments.

Table 3.7. TRG Register bit assignments
BitsNameFunction
[31:0][a]TRG

This count represents the number of 32-bit words between a TRIGIN or trigger packet and a Trigger Event.

[a] The width of this register is dependent on the TMC configuration.


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