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A.1. Signal descriptions

Table A.1 shows the ETM-A7 macrocell signals in alphabetical order.

Table A.1. ETM-A7 signals
AFREADYOutputATB interface FIFO flush finished.
AFVALIDInputATB interface FIFO flush request.
ASICCTL[7:0]OutputContents of ASICCTL Register.
ATBYTES[2:0]OutputSize of ATDATA.
ATCLKENInputClock enable for ATB interface.
ATDATA[63:0]OutputATB interface data.
ATID[6:0]OutputATB interface trace source ID.
ATREADYInputATDATA can be accepted.
ATVALIDOutputATB interface data valid.
CLKInputETM clock. Same as Cortex-A7 MPCore processor clock.
CLKCHANGEInputClock change indicator input. It is used when either the processor clock period or timestamp period changes.
CORESELECT[2:0]OutputETMA7 does not support multiple processor sharing the same ETM.

Indicates that the processor is in debug state.

This signal is connected to the processor general purpose DBGACK output, so that it can be used to determine when ETMDBGRQ can be deasserted. It is also used for other purposes in the ETM, and care must be taken to ensure the timing of this signal is appropriate because it does not come through the main interface between the processor and the ETM.


Invasive debug enable.

When HIGH, indicates that invasive debug is enabled.

DFTRSTDISABLEInputReset synchronization bypass DFT signal.
DFTSEInputScan enable DFT signal.

Current value of the processor Context ID Register.

ETMDA[31:0]InputAddress for data transfer.
ETMDBGRQOutputRequest from the macrocell for the processor to enter debug state. This must be ORed with any ASIC-level DBGRQ signals before being connected to the processor EDBGRQ input.
ETMDCTL[10:0]InputData control signals.
ETMDD[63:0]InputContains the data value for load, store, or coprocessor instructions.
ETMENOutputEnable signal for trace output from the ETM, driven by bit[11] of the ETMCR.
ETMIA[31:1]InputAddress for executed instruction.
ETMICTL[20:0]InputInstruction control signals.

When HIGH, indicates that the macrocell is in use.

When LOW:

  • external logic supporting the macrocell can be clock-gated to conserve power

  • the Cortex-A7 MPCore processor disables the interface

  • logic within the macrocell is clock-gated to conserve power.

ETMPWRUPREQ OutputThis signal is not used in the ETM-A7 macrocell because it is in a single power domain shared with the rest of the CoreSight debug system.
ETMSTANDBYWFXOutputIndicates that the macrocell FIFO is empty and that the Cortex-A7 MPCore processor can be put in Standby mode.
ETMVMID[7:0]InputCurrent value of the processor VMID.
ETMWFXPENDINGInputIndicates that the Cortex-A7 MPCore processor is about to go into Standby mode, and that the ETM must drain its FIFO.
EXTIN[3:0]InputExternal input resources.
EXTOUT[1:0]OutputExternal outputs.

For validation purposes only.

Indicates when various events occur before being written to the FIFO.

MAXCORES[2:0]InputNumber of processors the ETM can trace when in share mode. Ignored for ETMA7 since share mode not supported.

Number of external inputs the ASIC supports, maximum four.

These signals determine the value bits[19:17] in the ETMCCR, see Configuration Code Register.


Number of external outputs the ASIC supports, maximum two.

These signals determine the value bits[22:20] in the ETMCCR, see Configuration Code Register.


Non-invasive debug enable.

When HIGH, indicates that non-invasive debug is enabled.


Power-on reset. This is the main reset.


Debug APB address bus.


Indicates an external debug request from the Debug Access Port (DAP):

  • PADDRDBG31 at logic 1 indicates an access from hardware (JTAG)

  • PADDRDBG31 at logic 0 indicates an access from software.

PCLKENDBGInputDebug APB clock enable.
PENABLEDBGInputThe Debug APB interface is enabled for a transfer.
PMUEVENT[29:0]InputGives the status of the performance monitoring events. Used as extended external inputs.
PRDATADBG[31:0]OutputDebug APB read data.
PREADYDBGOutputUsed to extend Debug APB transfers.
PSELDBGInputDebug APB slave select signal.
PSLVERRDBGOutputDebug APB slave error.
PWDATADBG[31:0]InputDebug APB write data.

Debug APB transfer direction:





SYNCREQInputRequest for periodic synchronization.
TRIGGEROutputTrigger request status signal. Asserted for one clock cycle when a trigger occurs.
TSVALUEB[63:0]InputTimestamp value input bus.

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