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Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A
ChangeLocationAffects
No changes, first release--

Table B.2. Difference between Issue A and Issue B
ChangeLocationAffects
Correction to signal name capitalization and signal directions.Chapter 2 Functional OverviewAll revisions
Correction to signal name capitalization and signal directions.Appendix A Signal DescriptionsAll revisions
Clarification of management register descriptionChapter 3 Programmers ModelAll revisions
Component revision updated in the identification registersChapter 3 Programmers Modelr1p0
ATB replicator IDFILTER0 diagram updatedFigure 3.57All revisions
Moved and updated DAPBUS interconnect and APB interconnect and ROM table chapters into subsections of the Debug Access PortChapter 4 Debug Access PortAll revisions
Component versions updated in block summaryCoreSight SoC block summaryr1p0 and above
Detail added on clock domain crossing bridgesChapter 4 Debug Access PortAll revisions
Detail added on clock domain crossing bridgesChapter 5 ATB Interconnect ComponentsAll revisions
Detail added on clock domain crossing bridgesChapter 6 Timestamp ComponentsAll revisions
Event Asynchronous Bridge component information includedEntire documentAll revisions
Granular Power Requestor component added and referenced in Granular Power Requestor and Granular power requestor signalsChapter 10 Granular Power Requestorr1p0 and above
Timestamp interpolator component added and referenced in Timestamp interpolator and Timestamp interpolator signalsTimestamp interpolatorr1p0 and above

Table B.3. Difference between Issue B and Issue C
ChangeLocationAffects
Updated Structure of CoreSight SoC section.Chapter 1 IntroductionAll revisions
Updated Narrow timestamp asynchronous bridge revision in CoreSight SoC block summary.Chapter 1 IntroductionAll revisions
Updated Product revisions for r2p0.Chapter 1 Introductionr2p0
Added rombaseaddrl[31:0] and rombaseaddru[31:0] to Figure 2.6.Chapter 2 Functional OverviewAll revisions
Added rombaseaddr[31:0] to Figure 2.7.Chapter 2 Functional OverviewAll revisions
Updated Event asynchronous bridge section.Chapter 2 Functional OverviewAll revisions
Moved and updated JTAG-DP register summary into subsection of the Debug port register summary. Chapter 3 Programmers ModelAll revisions
Moved and updated JTAP-DP register descriptions into subsection of the Debug port implementation specific registers. Chapter 3 Programmers ModelAll revisions
Reset value correction in JTAG-DP register summary.Chapter 3 Programmers ModelAll revisions
Updated the description in Table 3.225.Chapter 3 Programmers ModelAll revisions
Updated the description in Table 3.235.Chapter 3 Programmers ModelAll revisions
Component revision updated in the identification registers.Chapter 3 Programmers Modelr2p0
Updated DAP flow of control section.Chapter 4 Debug Access PortAll revisions
Moved and updated Operation in JTAG-DP mode and Operation in SW-DP mode into subsection of the JTAG and SWD interface. Chapter 4 Debug Access PortAll revisions
Updated Table 5.4 in ATB upsizer section.Chapter 5 ATB Interconnect ComponentsAll revisions
Updated Arbitration section in ATB funnel.Chapter 5 ATB Interconnect ComponentsAll revisions
Added rombaseaddrl[31:0] and rombaseaddru[31:0] to Table A.6.Appendix A Signal DescriptionsAll revisions
Added rombaseaddr[31:0] to Table A.7.Appendix A Signal DescriptionsAll revisions