|TRACECLKIN||Input||Decoupled clock from ATB to enable easy control of the trace port speed. This is typically derived from a controllable clock source on chip but can be driven by an external clock generator if a high speed pin is used. Data changes on the rising edge only. See Off-chip based TRACECLKIN for more details of off-chip operated TRACECLKIN.|
|TRACECLK||Output||Exported version of TRACECLKIN. This is TRACECLKIN/2, and data changes on both rising edges and falling edges. See TRACECLK generation for more details about TRACECLK generation.|
|TRACEDATA[MPS:0]||Output||Output data. MPS is TPMAXDATASIZE.|
Used to indicate non valid trace data and triggers. See Other TPIU design considerations.
|TRESETn||Input||This is a reset signal for the TRACECLKIN domain. Because off-chip devices connect to the Trace Out port, this signal is related to the Trace Bus Resetting signal, ATRESETn.|
|TPCTL||Input||ASIC tie-off to report the presence of the TRACECTL pin. If TRACECTL is not present then this must be tied LOW. This input affects bit 2 of the Formatter and Flush Status Register.|
|TPMAXDATASIZE[4:0]||Input||Tie-off to indicate the maximum TRACEDATA width
available on the ASIC. The valid values are 1-32 (|