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8.2. Trace Out Port

Table 8.1 shows the Trace Out Port signals. For more information about TPIU registers, see Chapter 3 Programmers Model.

Table 8.1. Trace Out Port signals
NameTypeDescription
TRACECLKINInputDecoupled clock from ATB to enable easy control of the trace port speed. This is typically derived from a controllable clock source on chip but can be driven by an external clock generator if a high speed pin is used. Data changes on the rising edge only. See Off-chip based TRACECLKIN for more details of off-chip operated TRACECLKIN.
TRACECLKOutputExported version of TRACECLKIN. This is TRACECLKIN/2, and data changes on both rising edges and falling edges. See TRACECLK generation for more details about TRACECLK generation.
TRACEDATA[MPS:0]OutputOutput data. MPS is TPMAXDATASIZE.
TRACECTLOutput

Used to indicate non valid trace data and triggers. See Other TPIU design considerations.

TRESETnInputThis is a reset signal for the TRACECLKIN domain. Because off-chip devices connect to the Trace Out port, this signal is related to the Trace Bus Resetting signal, ATRESETn.
TPCTLInputASIC tie-off to report the presence of the TRACECTL pin. If TRACECTL is not present then this must be tied LOW. This input affects bit 2 of the Formatter and Flush Status Register.
TPMAXDATASIZE[4:0]InputTie-off to indicate the maximum TRACEDATA width available on the ASIC. The valid values are 1-32 (0x00-0x1F), for example if only a maximum of a 16-bit data port is available then this takes the value 0x0F. This input affects the Supported Port Size Register.