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Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A
Change Location Affects
First release - -

Table B.2. Differences between Issue A and Issue B
Change Location Affects
Correction to signal name capitalization and signal directions. Chapter 2 Functional Overview All revisions
Correction to signal name capitalization and signal directions. Appendix A Signal Descriptions All revisions
Clarification of management register description. Chapter 3 Programmers Model All revisions
Component revision updated in the identification registers. Chapter 3 Programmers Model r1p0
ATB replicator IDFILTER0 diagram updated. Figure 3.52 All revisions
Moved and updated DAPBUS interconnect and APB interconnect and ROM table chapters into subsections of the Debug Access Port. Chapter 4 Debug Access Port All revisions
Component versions updated in block summary. CoreSight SoC-400 block summary r1p0 and above
Detail added on clock domain crossing bridges. Chapter 4 Debug Access Port All revisions
Detail added on clock domain crossing bridges. Chapter 6 ATB Interconnect Components All revisions
Detail added on clock domain crossing bridges. Chapter 7 Timestamp Components All revisions
Event Asynchronous Bridge component information included. Entire document All revisions
Granular Power Requester component added and referenced in Granular Power Requester and Granular power requester signals. Granular Power Requester r1p0 and above
Timestamp interpolator component added and referenced in Timestamp interpolator and Timestamp interpolator signals. Timestamp interpolator r1p0 and above

Table B.3. Differences between Issue B and Issue C
Change Location Affects
Updated Structure of CoreSight SoC-400 section. Chapter 1 Introduction All revisions
Updated Narrow timestamp asynchronous bridge revision in CoreSight SoC-400 block summary. Chapter 1 Introduction All revisions
Updated Product revisions for r2p0. Chapter 1 Introduction r2p0
Added rombaseaddrl[31:0] and rombaseaddru[31:0] to Figure 2.6. Chapter 2 Functional Overview All revisions
Added rombaseaddr[31:0] to Figure 2.7. Chapter 2 Functional Overview All revisions
Updated Event asynchronous bridge section. Chapter 2 Functional Overview All revisions
Moved and updated JTAG-DP register summary into subsection of the Debug port register summary. Chapter 3 Programmers Model All revisions
Moved and updated JTAG-DP register descriptions into subsection of the Debug port implementation-specific registers. Chapter 3 Programmers Model All revisions
Reset value correction in JTAG-DP register summary. Chapter 3 Programmers Model All revisions
Updated the description in Table 3.218. Chapter 3 Programmers Model All revisions
Updated the description in Table 3.229. Chapter 3 Programmers Model All revisions
Component revision updated in the identification registers. Chapter 3 Programmers Model r2p0
Updated DAP flow of control section. Chapter 4 Debug Access Port All revisions
Moved and updated Operation in JTAG-DP mode and Operation in SW-DP mode into subsection of the JTAG and SWD interface. Chapter 4 Debug Access Port All revisions
Updated ATB upsizer section. Chapter 6 ATB Interconnect Components All revisions
Updated Arbitration section in ATB funnel. Chapter 6 ATB Interconnect Components All revisions
Added rombaseaddrl[31:0] and rombaseaddru[31:0] to Table A.7. Appendix A Signal Descriptions All revisions
Added rombaseaddr[31:0] to Table A.8. Appendix A Signal Descriptions All revisions

Table B.4. Differences between Issue C and Issue D
Change Location Affects

Updated the signal case for the following block diagrams:

Chapter 2 Functional Overview All
Updated the offset value for CIDR 0-3 in Table 3.246 Chapter 3 Programmers Model All
Updated the top-level signal case for ECT components.

Chapter 8 Embedded Cross Trigger

All
Updated the top-level signal case for TPIU components. Chapter 9 Trace Port Interface Unit All
Updated the top-level signal case for ETB components. Chapter 10 Embedded Trace Buffer All
Updated the top-level signal case for ECT, TPIU, and ETB components. Appendix A Signal Descriptions All
Updated the component version references

Table 1.1

Table 3.51

All

Table B.5. Differences between Issue D and Issue E

Change

Location

Affects

Updated product name to CoreSight SoC-400 Entire document

All

Added compliance information

Compliance

All

Updated signals Figure 2.6

All

Updated Debug Base Register descriptions All
Updated reset value for DOMAIN field AXI-AP Control/Status Word register r3p0
Updated figure to show JTAG-DP Figure 3.217 All
Modified the revision value in AHB-AP Identification register Table 3.219 r3p0
Added a note for Domain field in AXI-AP CSW register Table 3.220 r3p0
Updated ARLOCK and AWLOCK sizes AXI transfers All
Added synchronization request signals

All


Table B.6. Differences between Issue E and Issue F
Change Location Affects
Corrected case of signals. Throughout All
Updated the component block versions.

Chapter 1 Introduction

Chapter 3 Programmers Model

r3p1
Updated the example CoreSight SoC-400 system.

Typical CoreSight SoC-400 system

All
Improved clarity of the introduction.

Chapter 1 Introduction

All
Improved clarity of component descriptions in the functional overview, and redistributed information between this document, the ARM® CoreSight™ SoC-400 Integration Manual, and the ARM® CoreSight™ SoC-400 Implementation Guide to better match the intended audience of each document.

Chapter 2 Functional Overview

All
Moved APB component descriptions from DAP component descriptions to their own sections and chapter.

Chapter 2 Functional Overview

Chapter 4 Debug Access Port

Chapter 5 APB Interconnect Components

Appendix A Signal Descriptions

All
Moved event asynchronous bridge description from authentication bridges to cross-triggering components.

Chapter 2 Functional Overview

Chapter 8 Embedded Cross Trigger

Appendix A Signal Descriptions

All
Changed dapaddr[7:2] to dapcaddr[7:2].

AXI access port

Table A.7

r3p1
Removed ts_bit_valid_qualify signal from narrow timestamp replicator.

Narrow timestamp replicator

Narrow timestamp replicator

Table A.23

r3p1
Corrected timestamp interpolator signal list.

Timestamp interpolator

Table A.28

All
Added description of the authentication replicator.

Authentication bridges

Authentication and event bridges

All
Improved clarity of various programmers model registers. Chapter 3 Programmers Model All
Replaced SW-DP description of IDCODE register with DPIDR Register. Debug port implementation-specific registers All
Renamed SW-DP WCR Register to DLCR Register. Debug port implementation-specific registers All
Added description of Timestamp generator CNTCVL and CNTCVU registers.

Timestamp generator registers description

All
Reorganized, consolidated and rewrote substantial information in the component description chapters to improve clarity.

Chapter 4 Debug Access Port

Chapter 5 APB Interconnect Components

Chapter 6 ATB Interconnect Components

Chapter 7 Timestamp Components

Chapter 8 Embedded Cross Trigger

Chapter 9 Trace Port Interface Unit

Chapter 10 Embedded Trace Buffer

All

Added and corrected information on clocks and resets for each component.

Described where synchronizers are required.

Added note to consult the ARM® CoreSight™ SoC-400 Integration Manual, when using clock enables to interface between synchronous clock domains.

Chapter 4 Debug Access Port

Chapter 5 APB Interconnect Components

Chapter 6 ATB Interconnect Components

Chapter 7 Timestamp Components

Chapter 8 Embedded Cross Trigger

Chapter 9 Trace Port Interface Unit

Chapter 10 Embedded Trace Buffer

All
Clarified the behavior of low power interfaces.

Chapter 5 APB Interconnect Components

Chapter 6 ATB Interconnect Components

Chapter 7 Timestamp Components

All
Renamed SProt to CSW.Prot[1], because SProt is not defined elsewhere.

Chapter 4 Debug Access Port

Chapter 5 APB Interconnect Components

Chapter 6 ATB Interconnect Components

All
Corrected arbitration behavior of the non-programmable funnel. Non-programmable funnel All
Described use of ATB synchronous bridge as a trace buffer. ATB synchronous bridge All
Described usage of the timestamp distribution network for processor time and CoreSight time, and clarified that the same network must not be used for both. Chapter 7 Timestamp Components All
Clarified usage of the timestamp generator hltdbg signal. Timestamp generator All
Updated guidance to TPA designers on traceclk alignment expectations. traceclk alignment All
Added flowcharts from CoreSight Design Kits explaining ETB trace stop, flush, and trigger operation. ETB trace capture and formatting All
Removed Granular Power Requester chapter from the book, because the information is provided in Granular Power Requester and other sections. Chapter 2 Functional Overview All
Corrected CTM signal list to show that its channel interfaces are always four channels wide. Table A.30 All
Listed signals that must be connected between slave and master interface components of asynchronous bridges when separately implemented Appendix A Signal Descriptions All

Table B.7. Differences between Issue F and Issue G

Change

Location

Affects

Updated CoreSight block summary table. Table 1.1 r3p2
rombaseaddr port added to figure. Figure 2.8 r3p2
Added ATB Phantom Bridges section. ATB Phantom Bridges r3p2
Added Channel asynchronous bridge section.

Channel asynchronous bridge

Channel asynchronous bridge

r3p2
Added Cross Trigger to System Trace Macrocell section.

Cross Trigger to System Trace Macrocell

Cross Trigger to System Trace Macrocell

r3p2
Updated component revision fields. Chapter 3 Programmers Model r3p2
Added Timestamp recovery from stopped clock section. Timestamp recovery from stopped clock r3p2
Added description of JTAG instruction register configuration option. Serial Wire or JTAG Debug Port r3p2
Added missing Reset values column to table. Table 3.246 r3p2
Minor updates and corrections to text, figures and tables. Throughout the document. r3p2

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