The clock and reset signals of the TPIU are:
ATB interface clock. This is the main clock for the TPIU.
ATB interface clock enable.
ATB interface active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.
APB interface clock.
APB interface clock enable.
APB interface active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.
Trace out port source clock.
Trace out port active-LOW reset. This is asynchronously asserted and must be synchronously deasserted.
The TPIU includes an asynchronous bridge between the traceclkin clock domain and the rest of the design.
The TPIU requires the atclk and pclkdbg clocks to be synchronous, that is, clock tree balanced, with respect to each other. pclkdbg must be equivalent to, or an integer division of, atclk. If the pclkendbg and atclken clock enable inputs are used to change the effective update rate of the flip-flops in the TPIU then for each enabled pclkdbg edge, that is when pclkendbg = 1, there must be a corresponding enabled atclk edge.
An external asynchronous bridge can be used to bridge to an asynchronous domain if required.