Two high-density headers on the underside of the daughterboard route signal and power interconnects to the motherboard and to the other daughterboard site:
HDRYL routes signal and power interconnects to the motherboard.
HDRXL routes high-speed buses to the other daughterboard site.
an306_revb.xdc constraints file,
available in Application Note 306 Example LogicTile Express
20MG Design for a CoreTile Express A9x4.