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A.1.5. F-JTAG (ILA) connector

The V2F-1XV7 daughterboard provides an F-JTAG (ILA) connector, J4, to enable you to connect an ILA device, such as ChipScope, to debug designs in the FPGA. Figure A.4 shows the F-JTAG (ILA) connector.

Note

Pins 2, 4, 6, 8, and 10 on the F-JTAG (ILA) connector have pull-up resistors to 1V5.

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Table A.2 shows the F-JTAG (ILA) pin mapping for each ILA signal. the an306_revb.xdc constraints file, available in Application Note 306 Example LogicTile Express 20MG Design for a CoreTile Express A9x4, for FPGA mapping.

Table A.2. F-JTAG, ILA, connector, J4, signal list
Pin Signal Pin Signal
1 GND 2 ILA_1V5
3 GND 4 ILA_TMS
5 GND 6 ILA_TCK
7 GND 8 ILA_TDO
9 GND 10 ILA_TDI
11 GND 12 Not connected
13 GND 14 Not connected

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