You copied the Doc URL to your clipboard.

A.1.6. P-JTAG connector

The V2F-1XV7 daughterboard provides a P-JTAG connector to enable connection of RealView ICE, DSTREAM, or a compatible third-party debugger. Figure A.5 shows the P-JTAG connector, J18.

Note

DBGRQ has a pull-down resistor to 0V. DBGACK has no pull-up or pull-down resistor. All other signal connections on the P-JTAG connector have pull-up resistors to 1V5.

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table A.3 shows the P-JTAG pin mapping for each P-JTAG signal. the an306_revb.xdc constraints file, available in Application Note 306 Example LogicTile Express 20MG Design for a CoreTile Express A9x4, for FPGA mapping.

Table A.3. P-JTAG connector, J5, signal list
Pin Signal Pin Signal
1 VIREF 2 VSUPPLYA
3 nTRST 4 GND
5 TDI 6 GND
7 TMS 8 GND
9 TCK 10 GND
11 RTCK 12 GND
13 TDO 14 GND
15 nSRST 16 GND
17 DBGRQ 18 GND
19 DBGACK 20 GND

Was this page helpful? Yes No