This appendix describes the technical changes between released issues of this book.
|Clarified SATA pin and SATA FPGA mappings.||SATA connectors||All versions|
|Removed reference to Application Note AN306 because it does not include an example DDR3 controller netlist.||DDR3 memory interface (SO-DIMM)||All versions|
|SO-DIMM connector supports up to a maximum 4GB of external DDR3 RAM.||Rev C|
|Added section on information transmitted by the DCC to the motherboard||Voltage, temperature, oscillator, and SCC register monitoring||All versions|
|Clarified description of daughterboard clocks.||Table 2.7||All versions|
|Corrected description of PCI Express system.||All versions|