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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Issue A
Change Location Affects

No changes, first release

- -

Table C.2. Differences between Issue A and Issue B
Change Locations Affects
Clarified SATA pin and SATA FPGA mappings. SATA connectors All versions
Removed reference to Application Note AN306 because it does not include an example DDR3 controller netlist. DDR3 memory interface (SO-DIMM) All versions
SO-DIMM connector supports up to a maximum 4GB of external DDR3 RAM.

Overview of the daughterboard hardware

DDR3 memory interface (SO-DIMM)

Rev C

Table C.3. Differences between Issue B and Issue C
Change Locations Affects
Added section on information transmitted by the DCC to the motherboard Voltage, temperature, oscillator, and SCC register monitoring All versions
Clarified description of daughterboard clocks. Table 2.7 All versions

Table C.4. Differences between Issue C and Issue D
Change Locations Affects
Corrected description of PCI Express system.

System interconnect

PCI Express Bus (PCIe)

Figure 2.6

All versions

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