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2.5.2. Clock domains

Figure 2.6 shows the clock domains of the daughterboard.

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The GCLK_LOOP, XU_LOOP, and XL_LOOP clock loops enable you to use phase-shifted clocks internally in your design while transmitting the non phase-shifted clock externally. Application Note Example LogicTile Express 20MG Design for a CoreTile Express A9x4 contains an example use of phase-shifted clocks.

Note

Figure 2.6 shows the clocks available to implement the functions shown as blocks inside the FPGA. See the an306_revb.xdc constraints files, supplied in application note Application Note 306 Example LogicTile Express 20MG Design for a CoreTile Express A9x4. The application note implements the functions shown as solid blocks and does not supply the functions shown as dashed blocks.

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