The SB_GCLK1 and SMB_CLKO clocks, that connect to header HDRYL, and the SB_UP_GCLK1 and SMB_UP_CLK0 clocks, that connect to header HDRYU, are delay-matched global clocks. They connect between daughterboards in a stacked daughterboard system, and remain synchronous when received by FPGAs on the receiving daughterboards.
Figure 2.7 shows the global clocks on the V2F-1XV7 daughterboard.
The track lengths of global clocks on the V2F-1XV7 daughterboard are delay-matched to length L. The track lengths of the GCLK_LOOP clock loop is matched to length 2L. This enables two LogicTile Express 20MG, V2F-1XV7, daughterboards that are fitted on site 1 and site 2 of the motherboard to receive the MB_GCLK1 synchronous motherboard global clock.
Delay-matching enables vertical stacking of V2F-1XV7 daughterboards or custom design daughterboards that also have clock track matching of length L. This enables the GCLK_UP1 and SMB_CLK0 clocks to propagate up and down the stack synchronously. See Figure 2.8.
Figure 2.8 shows the recommended clocking scheme to distribute the global clocks to two stacked daughterboards.
Figure 2.9 shows the recommended clocking scheme to distribute the global clocks to three stacked daughterboards.
ARM recommends a maximum stack of three LogicTile Express 20MG on each motherboard site.
DDR FF are logic cells, and BUFG are buffers provided by Xilinx within the Virtex-7 FPGAs. This clocking scheme uses them to propagate the clocks with identical delays. See the Virtex-7 FPGA SelectIO Resources User Guide at the Xilinx web site for more information.