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2.5.1. Overview of clocks

Clock generators on the daughterboard, and inside the FPGA, generate the majority of the clocks that the daughterboard uses. Figure 2.6 shows the clock domains of the daughterboard.

The MCC transfers clock settings to the Daughterboard Configuration Controller during power-up sequencing using values that the daughterboard configuration files define. The Daughterboard Configuration Controller then configures the programmable clock generators.

The daughterboard has four on-board clock generators. You configure the frequencies of clock generators 1, 2 and 4 by editing the OSCCLKS section of configuration file an306r0p0.txt. See Application Note 306 Example LogicTile Express 20MG Design for a CoreTile Express A9x4 for an example an306r0p0.txt file.

Table 2.7 shows the daughterboard clocks.

Table 2.7. Daughterboard clocks
Daughterboard clocks Source Frequency range Comment
OSC[2:0] CLK GEN 1

2MHz-230MHz

1% resolution

Variables OSC0, OSC1, and OSC2 in file an306r0p0.txt configure these daughterboard clocks
OSC[4:3] CLK GEN 2

2MHz-230MHz

1% resolution

Variables OSC3, and OSC4 in file an306r0p0.txt configure these daughterboard clocks
OSC[5] - -

an306r0p0.txt contains variable OSC5 but the daughterboard does not use this clock

SATACLK0 CLK GEN 3 Fixed 150MHz -
SATACLK1 CLK GEN 4 Fixed 100MHz -
PCIE_UP_REFCLK(P|N) -
PCIE_UP_LOCAL_REFCLK(P|N) -
DDR3REFCLK

See an306r0p0.txt for a list of available frequencies.

Variables OSC6 in file an306r0p0.txt configures this daughterboard clock

See the ARM® Versatile™ Express Configuration Technical Reference Manual for information on how to edit daughterboard configuration files.

You can read and write to the daughterboard while the system is running using the motherboard SYS_CFG register interface.

See Figure 2.6.

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