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2.1. Overview of the daughterboard hardware

The hardware infrastructure supports system expansion and a number of debug interfaces. Figure 2.1 shows the high-level hardware infrastructure. For information on the connector signals to these additional interfaces, see Appendix A Signal Descriptions.

Note

The configuration image loaded into the FPGA at power-up defines the functionality of the daughterboard. Application Note 306 Example LogicTile Express 20MG Design for a CoreTile Express A9x4, provided by ARM, implements an example AMBA 3.0 system using the daughterboard.

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The hardware infrastructure of the daughterboard comprises:

  • One Xilinx Virtex-7 FPGA:

    • XC7V2000T-1 FPGA

    • 20 million gates.

    • Speed grade -1.

    • Gigabit transceiver connection to SATA connectors and to HDRYL and HDRYU headers.

  • One NAND Flash memory, used to store FPGA images.

  • A configuration EEPROM to store the board Hardware Board International (HBI) number and names of the current FPGA images.

  • One local Daughterboard Configuration Controller whose purpose is to:

    • Set the oscillator frequencies.

    • Set and monitor the power supply voltages.

    • Load the FPGA image.

    • Transfer SCC register values.

  • SO-DIMM memory connector:

    • 4GB of external DDR3 RAM fitted in the SO-DIMM connector that the FPGA drives.

  • One header connector, HDRXL, on the bottom side of the board for routing High-Speed Buses (HSBs) from the FPGA to the other daughterboard site on the motherboard:

    • One HSB Master, M, interface implemented on the FPGA.

    • One HSB Slave, S, interface implemented on the FPGA.

    • Low Voltage Differential Signaling (LVDS) support, 160 pairs.

    • 20 single-ended signals.

  • One header connector, HDRYL, for routing buses to the motherboard:

    • MultiMedia Bus (MMB).

    • PCI-Express Bus (PCIe).

    • System Bus (SB).

    • Static Memory Bus (SMB).

    • Configuration Bus (CB).

    • Gigabit transceiver connection.

  • Two header connectors, HDRXU and HDRYU, on the top side of the board to support upward expansion. The HDRYU header is only partly populated. See the an306_revb.xdc file in the docs directory of the DVD supplied with the V2F-1XV7 daughterboard:

    • 320 single-ended IO pins that you can configure as up to 160 pairs, LVDS, and 20 single-ended only IO pins available on the FPGA that connect to HDRXU.

    • 100 general, single-ended, IO pins available on the FPGA that connect to HDRYU.

  • Serial Advanced Technology Attachment (SATA) connectors:

    • Two Host, H, connector.

    • Two Device, D, connector.

    • Each connector has one transmit lane and one receive lane.

  • PCI-Express Bus (PCIe):

    • Configurable PCIe capability with a maximum capacity of 4 lanes upwards and 4 lanes downwards. See PCI Express Bus (PCIe).

  • Debug interfaces:

    • P-JTAG port for DSTREAM™ or other compatible third-party debuggers.

    • Integrated Logic Analyzer (ILA) F-JTAG port for ChipScope, for example.

    • One trace port supporting 16-bit trace.

  • Eight green general-purpose user LEDs, S0-S7, connected to the Daughterboard Configuration Controller.

  • One green user LED, FPGA_LED, connected to the FPGA.

  • One green FPGA DONE_LED, connected to the Daughterboard Configuration Controller.

    • Indicates FPGA configured.

  • One green power 3V3 power supply LED, 3V3_LED:

    • Indicates onboard 3V3 power supply operating inside its specified limits.

  • One red OverTemp LED, connected to the Daughterboard Configuration Controller:

    • Indicates FPGA over temperature.

    • This LED flashes briefly at daughterboard powerup.

  • Eight red FPGA power supply fault LEDs:

    • Each LED indicates FPGA power supply operating outside its specified limits.

    • These LEDs flash briefly at daughterboard powerup.

  • Eight general-purpose Dual In-Line Package (DIP) switches connected to the Daughterboard Configuration Controller.

  • One user switch connected to the FPGA.

  • A battery to provide power to the FPGA to store the FPGA image AES decryption key.

  • Five on-board programmable oscillators, all input to the FPGA.

For more information see System interconnect.

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