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3.2. Register summary

Table 3.1 shows the registers in offset order from the base memory address.

Table 3.1. Register summary

Offset

Name

Type

Reset

Width

Description

0x000-0x0FC DCC_CFGx RW 0xXXXXXXXX[a] 32 DCC_CFGx registers
0x100 DCC_LOCK RO 0xFFXX000X[b] 32 DCC_LOCK Register
0x104 DCC_LED RO 0x0000000F 32 DCC_LED Register
0x108 DCC_SW RO 0x00000000 32 DCC_SW Register
0xFF8 DCC_AID RO 0xXXXXXXXX[a] 32 DCC_AID Register
0xFFC DCC_ID RO 0xXXXXXXXX[a] 32 DCC_ID Register

[a] Where X = unknown at reset.

[b] Last X = b000X, either b0000 or b0001.


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