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A.10.1. Clock and configuration signals

Table A.10 shows the clock and configuration signals.

Table A.10.  Clock and configuration signals
SCLKENInputCHI interface bus clock enable
SINACTInputCHI snoop active
NODEID[6:0]InputCortex-A53 CHI Node Identifier
RXSACTIVEInputReceive pending activity indicator
TXSACTIVEOutputTransmit pending activity indicator
RXLINKACTIVEREQInputReceive link active request
RXLINKACTIVEACKOutputReceive link active acknowledge
TXLINKACTIVEREQOutputTransmit link active request
TXLINKACTIVEACKInputTransmit link active acknowledge
REQMEMATTR[7:0]OutputRequest memory attributes

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