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A.11. ACE interface signals

This section describes the ACE master interface signals:

For a complete description of the ACE interface signals, see the ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite.

Note

  • This interface exists only if the Cortex-A53 processor is configured to have the ACE interface.

  • All ACE channels must be balanced with respect to CLKIN and timed relative to ACLKENM.

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