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A.13.2. Miscellaneous debug signals

Table A.35 shows the miscellaneous Debug signals.

Table A.35. Miscellaneous Debug signals
SignalDirectionDescription
DBGROMADDR[39:12]Input

Debug ROM base address.

Specifies bits[39:12] of the ROM table physical address.

If the address cannot be determined, tie this signal LOW.

This pin is sampled only during reset of the processor.

DBGROMADDRVInput

Debug ROM base address valid.

If the debug ROM address cannot be determined, tie this signal LOW.

This pin is sampled only during reset of the processor.

DBGACK[CN:0]Output

Debug acknowledge:

0

External debug request not acknowledged.

1

External debug request acknowledged.

nCOMMIRQ[CN:0]Output

Communications channel receive or transmit interrupt request

0

Request interrupt.

1

No interrupt request.

COMMRX[CN:0]Output

Communications channel receive. Receive portion of Data Transfer Register full flag:

0

Empty.

1

Full.

COMMTX[CN:0]Output

Communication transmit channel. Transmit portion of Data Transfer Register empty flag:

0

Full.

1

Empty.

EDBGRQ[CN:0]Input

External debug request:

0

No external debug request.

1

External debug request.

The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK.

DBGEN[CN:0]Input

Invasive debug enable:

0

Not enabled.

1

Enabled.

NIDEN[CN:0]Input

Non-invasive debug enable:

0

Not enabled.

1

Enabled.

SPIDEN[CN:0]Input

Secure privileged invasive debug enable:

0

Not enabled.

1

Enabled.

SPNIDEN[CN:0]Input

Secure privileged non-invasive debug enable:

0

Not enabled.

1

Enabled.

DBGRSTREQ[CN:0]OutputWarm reset request.
DBGNOPWRDWN[CN:0]Output

No powerdown request:

0

On a powerdown request, the SoC power controller powers down the processor.

1

On a powerdown request, the SoC power controller does not power down the processor.

DBGPWRDUP[CN:0]InputProcessor powered up.
DBGPWRUPREQ[CN:0]Output

Power up request:

0

Power down debug request to the power controller.

1

Power up request to the power controller.

DBGL1RSTDISABLEInput

Disable L1 data cache automatic invalidate on reset functionality:

0

Enable automatic invalidation of L1 data cache on reset.

1

Disable automatic invalidation of L1 data cache on reset.

This pin is sampled only during reset of the processor.


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