Any error that is detected is reported in the CPUMERRSR or L2MERRSR registers. See CPU Memory Error Syndrome Register or L2 Memory Error Syndrome Register. Any error that is detected is also signalled on the PMUEVENT bus. See Events. This includes errors that are successfully corrected, and those that cannot be corrected. If multiple errors occur on the same clock cycle then only one of them is reported.
Errors that cannot be corrected, and therefore might result in data corruption, also cause an abort or external pin to be asserted, so that software can be aware that there is an error and can either attempt to recover or can restart the system:
Uncorrectable errors in the L2 data RAM when read by an instruction fetch, TLB pagewalk, or load instruction, might result in a precise data abort or prefetch abort.
Uncorrectable errors in the L1 or L2 data RAMs when the line is being evicted from a cache causes the nINTERRIRQ pin to be asserted. This might be because of a natural eviction, a cache maintenance operation, or a snoop.
Uncorrectable errors in the L2 tag RAMs or SCU L1 duplicate tag RAMs causes the nINTERRIRQ pin to be asserted.
When nINTERRIRQ is asserted it remains asserted until the error is cleared by a write of 0 to the L2 internal asynchronous error bit of the L2ECTLR register.
ARM recommends that the nINTERRIRQ pin is connected to the interrupt controller so that an interrupt or system error is generated when the pin is asserted.
When a dirty cache line with an error on the data RAMs is evicted from the processor, the write on the master interface still takes place, however if the error is uncorrectable then:
On ACE, the write strobes are not set, therefore the incorrect data is not written externally.
On CHI, the strobes are set, but the response field indicates that there is a data error.
When a snoop hits on a line with an uncorrectable data error the data is returned, if required by the snoop, but the snoop response indicates that there is an error.
If a snoop hits on a tag that has an uncorrectable error, then it is treated as a snoop miss, because the error means that it is unknown if the cache line is valid or not.
In some cases it is possible for an error to be counted more than once. For example, multiple accesses might read the location with the error before the line is evicted as part of the correction process.