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14.5.4. Component Identification Registers

There are four read-only Component Identification Registers, Component ID0 through Component ID3. Table 14.14 shows these registers.

Table 14.14. Summary of the Component Identification Registers
RegisterValueOffset
Component ID00x0D0xFF0
Component ID10x900xFF4
Component ID20x050xFF8
Component ID30xB10xFFC

The Component ID registers are:

Component Identification Register 0

The CTICIDR0 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTICIDR0 by condition code is:

Off DLKOSLKEPMADSLKDefault
----RORO

Table 14.4 describes the condition codes.

Configurations

CTICIDR0 is in the Debug power domain.

CTICIDR0 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.9 shows the CTICIDR0 bit assignments.

Figure 14.9. CTICIDR0 bit assignments

Figure 14.9. CTICIDR0 bit assignments

Table 14.15 shows the CTICIDR0 bit assignments.

Table 14.15. CTICIDR0 bit assignments
BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]PRMBL_0
0x0D

Preamble byte 0.


CTICIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF0.

Component Identification Register 1

The CTICIDR1 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTICIDR1 by condition code is:

Off DLKOSLKEPMADSLKDefault
----RORO

Table 14.4 describes the condition codes.

Configurations

CTICIDR1 is in the Debug power domain.

CTICIDR1 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.10 shows the CTICIDR1 bit assignments.

Figure 14.10. CTICIDR1 bit assignments

Figure 14.10. CTICIDR1 bit assignments

Table 14.16 shows the CTICIDR1 bit assignments.

Table 14.16. CTICIDR1 bit assignments
BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]CLASS
0x9

Debug component.

[3:0]PRMBL_1
0x0

Preamble byte 1.


CTICIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF4.

Component Identification Register 2

The CTICIDR2 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTICIDR2 by condition code is:

Off DLKOSLKEPMADSLKDefault
----RORO

Table 14.4 describes the condition codes.

Configurations

CTICIDR2 is in the Debug power domain.

CTICIDR2 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.11 shows the CTICIDR2 bit assignments.

Figure 14.11. CTICIDR2 bit assignments

Figure 14.11. CTICIDR2 bit assignments

Table 14.17 shows the CTICIDR2 bit assignments.

Table 14.17. CTICIDR2 bit assignments
BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]PRMBL_2
0x05

Preamble byte 2.


CTICIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF8.

Component Identification Register 3

The CTICIDR3 characteristics are:

Purpose

Provides information to identify a CTI component.

Usage constraints

The accessibility of CTICIDR3 by condition code is:

Off DLKOSLKEPMADSLKDefault
----RORO

Table 14.4 describes the condition codes.

Configurations

CTICIDR3 is in the Debug power domain.

CTICIDR3 is optional to implement in the external register interface.

Attributes

See the register summary in Table 14.3.

Figure 14.12 shows the CTICIDR3 bit assignments.

Figure 14.12. CTICIDR3 bit assignments

Figure 14.12. CTICIDR3 bit assignments

Table 14.18 shows the CTICIDR3 bit assignments.

Table 14.18. CTICIDR3 bit assignments
BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]PRMBL_3
0xB1

Preamble byte 3.


CTICIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC.

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